ICGITS' 2013 - Electronics & Communication Engineering

Assymetrical full bridge converter for photovoltaic systems[ ]


This paper describes a step-up DC-DC converter, which main task is to increase the voltage from a low level drawn from a photovoltaic (PV) panel, to a high controlled level for a connected inverter. Photovoltanic cell operated with a maximum power point tracking technique.The converter also provides an electrical isolation of PV panels from the grid. In the DC-DC converter asymmetrical full bridge converter topology is used. The converter operates at high switching frequency to achieve small size of the power transformer. The main benefit of this converter is zero-voltage switching (ZVS) of primary MOSFETs and zero-current switching (ZCS) of rectifier diodes over the entire operating range. Advantage of used topology is that the converter can be controlled by a simple 8bit microcontroller (MCU). A simulated model with maximum efficiency was built to verify properties of the asssymetrical full bridge converter DC-DC converter.

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Design and Simulation of AC to DC Low Voltage Energy Harvesting Converters[ ]


In this paper, an ac/dc converter is presented that can boost very low ac voltages to a higher dc voltage. The converter is based on a new hybrid form of boost converter and a buck boost converter and it is suitable for power harvesting applications too. The measured prototype can supply 3.3V by converting an input voltage of 400mV delivered by an electromagnetic microgenerator. Detailed analysis of converter is carried out .Further; the converter is simulated with both PI control and Fuzzy control. Control algorithm using fuzzy control is described in detail. Using the simulated output waveform, comparison between PI and Fuzzy is done.

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Buck & Boost(Mix-Voltage) Operation Of Single Inductor Dual Output Buck Converters[ ]


A single-inductor dual-output (SIDO) buck converter has recently found applications in hand-held battery-powered devices. . The circuit operation and its functional interdependences among basic converter parameters such as voltage gains, duty cycles, and current values are much more complicated than those of the single-output buck converters. In this paper, certain analysis was conducted to develop dc equations in steady state operation for SIDO buck converters. In addition to this , from the analysis results, a new operating mode “mix-voltage” operation is mentioned and in “mix-voltage” operating mode, the converter can work even when the input voltage is lower than maximum of the two output voltages. Earlier, a SIDO buck converter is used for providing “pure-buck” outputs which means that both output voltages are lower than the input voltage. So that,this possibility opens up new applications in existing applications.

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Quasi Z-Source Inverter with Enhanced Voltage Gain for Photovoltaic Power Generation[ ]


A quasi-Z-source inverter with a novel carrier based pulse width modulation (PWM) scheme is proposed for photovoltaic power generation systems. In this new technique, a high frequency sine wave is employed as carrier waveform instead of the conventional triangular wave in the simple boost technique. This increasess the shoot-through duty cycle for the given modulation index and hence the voltage gain. This paper manifests that the quasi-Z-source inverter employing this new PWM can boost DC voltage to the desired level and working as a power conditioning system to achieve the maximum power from photovoltaic array. The proposed control scheme is analyzed to exhibit the novelty of features. The control algorithm is affirmed by simulation and experimental results.

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THD Minimization on the Line to Line Voltage of Multilevel Inverters[ ]


In this paper, minimization of the total harmonics (THD) present in the output voltage of multilevel inverters is discussed . In order to reduce the harmonic contents of the inverter's output voltage the best approach is THD minimization. In multilevel inverters, if fundamental frequency switching strategy is considered,(each switch turning on and off once per output cycle), the switching angles can be selected so that the output THD is minimized. To obtain the optimum switching angles, an optimization algorithm is applied to the output-voltage THD. In the case of three-phase multilevel inverters, the optimization algorithm is generally applied to the phase voltage of the inverter. This results in the minimum THD in phase voltage but not necessarily in the line-to-line minimum THD. In three-phase applications, the line-voltage harmonics are of the main concern from the load point of view. In this paper, using the genetic algorithm and sinusoidal PWM technique, a THD minimization process is applied to the line-to-line voltage of the inverter. This paper is based on a comparison between seven level cascaded and nine level diode clamped multilevel inverter.

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Partial Discharge Detection in Solid Dielectrics[ ]


Partial Discharge (PD) measurement and characterization provide vital information on insulation condition, different aspects of insulation ageing useful for equipment integrity verification and diagnosis. The work demonstrates standard test methods which employs capture of PD parameters with the aid of discharge detector. This paper investigates on the voltage amplitude at which PD of a specified magnitude commence and determines the apparent charge, discharge energy and power dissipation for discharge quantity at a specified voltage. PD detection and measurement procedures suitable for use on Current Transformers, Insulators and Air Break (AB) switches are examined.

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Energy Management in Smart Buildings with Intelligent Control Systems [ ]


Commercial buildings have increased energy demand with lot of energy wastage. Energy efficiency of such buildings can be increased by properly managing the energy. For the same, an Intelligent Energy Management System (EMS) introduced in a commercial building aims to improve environment within the building to ensure customers’ comfort. The control system for such a building minimizes the power consumption without compromising the customers’ comfort. An intelligent multi-agent control system for energy and comfort management in the smart building serves this purpose. Increased challenges faced by the modern power systems include increased energy demand, environmental concerns etc. The utility along cannot meet all these challenges. Microgrid, which uses renewable energy sources, is a solution for the same. The energy management system, its control and the simulation results show the effectiveness of the energy management system.

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Fault Analysis and Digital Protection of Busbars Using Curvelet Transform Based Approach[ ]


The reliability and stability of a power system depends to a great extent on the efficiency of busbar protection scheme. The proposed protection scheme makes use of curvelet transform based analysis. Curvelet transform overcomes the weakness of wavelets in higher dimensions and will better capture the curve singularities and hyper plane singularities of high dimensional signals. The detail and fine coefficients of curvelets are strongly orientation sensitive, which is a useful property for detecting curves in signals. The proposed algorithm was tested using the busbar modeled in Simulink and simulating various fault conditions. The signal analysis was done by using wrapping based fast discrete curvelet transform. Results presented in this paper showed the capability of implementing a busbar protection scheme using the proposed approach.

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Optimal Power flow with FACTS devices using Genetic Algorithm[ ]


Increasing demands for reliable and most economic operation of transmission and distribution systems has been met by the use of FACTS devices. The paper incorporates Optimal power flow with FACTS device embedded in transmission line that constitute a valuable tool in operations of meeting these high demands. Optimal power flow with FACTS devices belong to a class of nonlinear constrained optimization problem with generation cost and system losses as the objective functions. The genetic algorithm approach is used to achieve optimal power flow in power system incorporating FACTS device. Genetic algorithm determines the control parameters of power flow constraints with FACTS devices. The various parameters considered are the location of Facts devices, their type and rating. Static power flow models are developed for Static Var Compensator (SVC), Thyristor Controlled Series Compensator (TCSC), and Unified Power Flow Controller (UPFC) using Power injection method. These equations are embedded into normal Newton Raphson equations to form extended Newton Raphson Power flow with FACTS devices. In the paper Genetic algorithm is coupled with full ac power flow equations which selects best regulation to minimize total generation cost keeping power flow within limits. MATLAB coding is developed for simulation .The algorithm is being applied to an IEEE 30 bus system.

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Transient Stability Analysis of Wind Integrated Power Systems with Central Area Controller[ ]


It is widely accepted that transient stability is an important aspect in designing and upgrading electric power system. This paper covers the modeling and the transient stability analysis of the wind integrated IEEE 14 test bus system using Matlab Power System Analysis Toolbox (PSAT) package. A three-phase fault is applied in the test system and stability is analyzed. Later, area controller is implemented to analyze the system stability. The evaluation is illustrated by conducting two case studies, modified IEEE-14 bus system and southern Kerala grid. It was observed that addition of area controller improves the system stability and thereby the power system performance.

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Performance Analysis of Conventional and Intelligent Controllers In Power Systems With AGC[ ]


large scale power systems are normally composed of control areas or regions representing coherent groups of generators. Area load changes and abnormal conditions lead to mismatches in frequency and scheduled power interchanges between areas. These mismatches have to be corrected by Automatic Generation Control (AGC), which is defined as the regulation of the power output of generators within a prescribed area. In this paper, the system investigated consists of two area thermal systems. A model of the same with conventional PI and PID controller is developed in MATLAB/SIMULINK and responses of change in frequency, tie line power and change in mechanical power are observed. Tuning of PI and PID controllers are done using Ziegler-Nichols tuning method. The later part of the study involves replacing the conventional controller with Fuzzy Logic Controller (FLC). After comparing the dynamic responses with the one obtained from the conventional controllers, Fuzzy logic controller is found to be a best controller than the conventional controllers.

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wireless power transmission using evanescent signals for mobile charging[ ]


With Wireless electricity (Witricity), transfer of power across large air gaps have been achieved to power both small and large equipments. Evanescent coupling using magnetic resonance allows power transfer with high efficiency. In this paper, analysis has been done on the various technol-ogies using equivalent circuits which are a familiar format of electrical engineers. Magnetic resonance has been used to transfer power to a mobile phone at a vertical distance of 15cm from a table top. The source antenna coil was powered using a DC-AC oscillator coupled to a power amplifier. The device antenna coil was connected to rectifier and a regulator to power the mobile. An operating power gain of 19.23% was realized.

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Analysis of Voltage Collapse in the Largest Grid Substation in Kerala[ ]


Kerala State Electricity Board (KSEB) the main power generators in Kerala uses breaker switched capacitor for voltage support and reactive power compensation in the largest Grid substation at Kalamassery. The capacitor bank installed at Kalamassery does not meet the system requirement. This lead to a Voltage Collapse in the Kalamassery area. In order to avoid this problem some FACTS devices are employed at the load centre. FACTS devices are used as a reactive power source and the optimal location for these devices were found out. The criterion used is based on the voltage profile of the system, that is the voltage deviation at each bus with respect to its optimum value is minimized. The modeling of the system was done using Power System Analysis Toolbox(PSAT) and a Power flow analysis was also carried out. The results shows that the method works effectively and is applicable to practical network.

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Mitigation of Symmetrical and Nonsymmetrical Deep Voltage Sag Swell and Phase Jump Using Dynamic Voltage Restorer (DVR) With Pre Sag Compensation Technique[ ]


The voltage sags and swells are important power quality problems and the Dynamic Voltage Restorer ( ), is the effective device to mitigate the large voltage sags and swells. In this paper deals with a DVR with Rectifier Supported dc-dc Boost Converter or a deep voltage-sag or swell compensator, which consists of a set of uncontrolled shunt, dc-dc boost and series converters connected back-to-back with three series injection transformers. The dc-dc boost converter installed for maintaining stabilized DC-link voltage which helps to mitigate deep voltage sag or swell. The DVR is characterized by installing the series converter on the source side and the shunt converter on the load side. Here elucidate the design procedure of the rectifier supported dc-dc boost converter DVR and analysis with emphasize to compensate the deep voltage sags or swells up to 50% and also compensate the phase jump. This control method is enough to protect the sensitive loads from supply disturbances. The DVR is operated in such a fashion that it does not supply or absorbed any active power during the steady-state operation; hence system will not make any additional power loss. The operations of dc-dc boost converter supported DVR are verified through extensive digital computer simulation studies.

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Estimating the Cost of Wind Power in a Restructured Power System Based on Locational Marginal Prices[ ]


This paper focuses in the economics of wind power markets by finding the supply and demand costs in the presence of transmission congestion and line losses. Wind producers are affected by the variable and stochastic nature of wind mills. In the Vertically integrated monopoly markets, conventional and non-conventional resources are correlated together so that it can result in the declared supply cost and demand cost to be equal. It is expected that after some decades, the installation of solar and tidal will decrease the inelastic wind power supplied to the consumers. This situation can be avoided by the proper selection of sites, implementation of exact costs, and calculation of perfect Locational Marginal Pricings (LMPs) based on congested and un-congested cases. This paper demonstrates the solutions by three sections. Firstly, the estimation for economics of wind power generation based on all the basic parameters needed for a wind power plant. Secondly, the analysis of supply (producers) and demand (consumers) in a two area networks for un-congested and congested systems. Finally, the identification of LMPs and line losses are intended with and without economic constraints. The MATLAB programs are simulated on the basis of demand and supply curves.

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RF Energy Harvesting System And Rectennas[ ]


Recent advances in ultra-low power wireless communications and energy-harvesting technologies have made self-sustainable devices feasible. Typically, the major concern for these devices is battery life and replacement. Applying energy harvesting techniques to these devices can significantly extend battery life and sometimes even eliminate the need for a battery. This technique is widely applicable in low power circuits such as wireless sensors. One emerging wireless sensor networks (WSN) application is in agriculture sector, where sensor nodes are deployed in fields to monitor humidity, temperature and soil moisture. Energy supply to such sensors is an issue as they are typically powered by conventional batteries which have a limited lifespan. Cost is often prohibitive when replacing exhausted batteries since the sensor devices need to be unearthed. An attractive solution is to use radio frequency (RF) energy harvesting, in which the radiated RF energy from ambient is extracted and converted into usable energy to power up the sensors.

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Analysis Of Transient Stability Of A Permanent Magnet Synchronous Generator Connected To Grid[ ]


The global energy consumption is rising and an increasing attention is being paid to alternative methods of electricity generation. The environmental impact of the renewable energy is very low and this makes them a very attractive solution for a growing demand. In this trend towards the diversification of the energy market, wind power is probably the most promising sustainable energy source, because of the relatively low capital cost involved and the short gestation period required. Induction generators used as wind generator are simple and easy to maintain. But the major drawback of this machine is its additional reactive burden on the system. Hence a variable speed wind generator such as a doubly fed induction generator or a permanent magnet synchronous generator (PMSG) is used. The fluctuating nature of wind causes the output of the variable speed PMSG to vary in amplitude and frequency, which is not suitable for use. Therefore in this work suitable control strategies are developed to produce a constant voltage and power and the transient stability analysis is carried out by simulating symmetrical and unsymmetrical fault as network disturbances. This is demonstrated using MATLAB simulations.

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Two Stage Grid Connected PV System Using Cuk Converter[ ]


In a grid connected photovoltaic system maximum power is to be drawn from the PV panel and has to be injected to the grid.For this various MPPT topologies and control methods are available. In a two stage stage system the loss factors such as fast irradiance variations, dc load variations, limited operating voltage range etc. cause zero loss but the use of additional converter causes extra loss in two stage system compared to the single stage grid connected system. As a result single stage grid connected systems are considered more efficient compared to the two stage systems in grid connected and stand alone applications. Thus in this paper, a Cuk converter is used instead of the boost converter that was used in the two stage conventional grid connected system. And as Cuk converter is having inductors at both input and output side it can reduce current ripples at both input and output sides, and it can also reduce the switching losses. Hence in this paper a Simulink model of two stage grid connected PV system using Cuk converter is presented. For tracking maximum power point the most common and accurate algorithm - incremental conductance algorithm is used. Inverter control is done using the DC bus voltage algorithm.

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A High Performance and Low Latency Fpga Implementation of Cordic Algorithm[ ]


CORDIC is generally faster than other approaches when a hardware multiplier (e.g., a microcontroller) is not available, or when the number of gates required to implement the functions it supports should be minimized (e.g., in an FPGA). On the other hand, when a hardware multiplier is available (e.g., in a DSP microprocessor), table-lookup methods and power series are generally faster than CORDIC. In recent years, the CORDIC algorithm has been used extensively for various biomedical applications, especially in FPGA implementations. Here we use Unfolded architecture for CORDIC in order to achieve low latency for rotation and various functions such as multiplication, division logarithmic exponential and trigonometric functions. The approach of this architecture provides high performance and low latency field programmable gate array implementation of rotational CORDIC algorithm. CORDIC device is highly suitable for computing many functions with precisely the same hardware, so they are ideal for applications with an emphasis on reduction of cost (e.g. by reducing gate counts in FPGAs) over speed and low clock rate can be utilized to meet low power consumption requirement.

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ASIC Based Design of High Speed Parallel MAC Based On Radix 4 & Radix 8 Booth Encoding[ ]


Real time signal processing applications are increasingly demanded now a day, which are used for multimedia, communication etc. . . . Speed is the major factor for the above application. Parallel MAC is an important element in digital signal processing, because they determine the execution time of the system, i.e. they have the highest delay among basic operational blocks. So in order to improve the speed of the system delay of MAC has to be decreased. This MAC provides high speed in multiplication and multiplication with accumulative addition than general MAC. This paper presents a parallel MAC based on radix-4 & radix-8 booth encodings. In this Paper, several methods to improve the speed of Parallel MAC has been checked, as a result Kogge Stone Ling Adder has been used instead of ordinary CLA to improve the speed.

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A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic[ ]


The increasing demand for low power VLSI can be fulfilled to a great extend by making proper changes in the circuit level and architectural level design. Addition is a fundamental operation, as it is used to implement more complex functions such as subtraction, multiplication, division etc. The Manchester Carry Chain adder design is preferred to other adders, regardless the number of bits because of its high-speed and is wide applications. A new technique is presented in this paper for the implementation of a 32 bit Adder which operates at low power. Even though this implementation is structurally inherited from Manchester Carry Chain based Adder, it is highly area efficient without much increase in delay. The proposed adder was based on Multiple Output Domino logic, which helps to reduce the complexity of the adder implemented using Manchester Carry Chain adder implemented in CMOS logic. At the same time, the 4T implementations of XOR based circuits in the adder design results in lesser number of transistors for its implementation and thereby provide a low power/size solution for arithmetic functions. The simulation result shows a reduction of 25% in size, over CMOS adder implemented using the same Manchester Carry Chain topology at 1.5v Supply voltage with the help of TSMC .18u technology.

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Optimization of stacked diaphragms for MEMS Piezoresistive pressure sensor[ ]


Micro Electro Mechanical System (MEMS) based silicon pressure sensors have undergone a significant growth in the last few years. In most of the cases, pressure sensors are manufactured by bulk micromachining or surface micromachining and square diaphragms of constant thickness in the order of microns are used. The sensitivity and linear deflection of pressure sensor highly depends upon the diaphragm structure. In this work, optimisation of the thickness of various layers for stacked silicon on insulator(SOI) diaphragms is studied. Also a study of the bulk micro machined silicon piezoresistive pressure sensor and a surface micro machined SOI pressure sensor are simulated and compared with respect to output voltage and deflection.

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A Fine Grain Power Gated FPGA with an Area Efficient High Speed Time Multiplexed Level Encoded Dual Rail Architecture[ ]


The most important challenge in the IC manufacturing industry is high performance with reduced power, area and cost. Asynchronous FPGAs have the advantages of lower power consumption, lower electromagnetic interference, and better modularity in large systems. This paper focusses on the reduction of dynamic power consumption of FPGAs for which two techniques are employed. Fine-grain power gating methods are used to decrease the power consumption. The implemented architecture projects a granularity size as fine as a single two-input and one-output lookup table. The proposed architecture directly detects the activity of each look-up-table by exploiting the advantageous features of asynchronous architectures. To add to this, the arrival of data is detected in advance and this prevents the increased delay required for the waking up of a logic block and the power consumption due to unnecessary switching. A comparison study between the existent and proposed dual rail encoding architectures shows that the newly implemented logic block with power gating and TM-LEDR encoding occupies lesser area and works at a greater speed as compared to the already existing conventional ones.

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Temperature Study of Reinforced MEMS Pressure Sensor[ ]


Micro Electro Mechanical Systems pressure sensors have been simulated with different parameters for obtaining wider operation range with better sensitivity. The performance has been simulated and analyzed for silicon and SOI (Silicon-on-Insulator) pressure sensors. The performance of silicon and SOI pressure sensor at a given pressure and temperature are compared. The doping concentration of the piezoresistor is varied from 1015 cm-3 to 10 20 cm-3 and the sensitivity of pressure sensors were compared. A comparative study of temperature sensitivity of silicon and SOI based diaphragms in the temperature from 150K to 500K has also been evaluated in this work

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Fixed Width Booth Multiplier using Error Compensation[ ]


In many multimedia and digital-signal processing (DSP) applications, multipliers are considered to be the basic arithmetic units. These multipliers significantly influence the system’s performance and power dissipation. To achieve high performance, the modified Booth encoding has been widely adopted in parallel multipliers. It reduces the number of partial products through performing multiplier re-coding. The number of adder cells in the Booth multiplier architecture can be reduced by various techniques. The process of truncation can be done so that the multiplier structure can be simplified to form a fixed width multiplier. The 2n bit product that is to be obtained from the multiplication of n bit multiplicand and n bit multiplier is truncated to n output bits by eliminating the adder cells needed for the addition of n least-significant bits (LSBs). The elimination of certain adder cells can cause truncation error. Hence, appropriate compensation biases are to be introduced into the retained adder cells. The compensation circuit needed for reducing truncation error is also designed here. Our proposed encoder was simulated in Mentor Graphics Model Sim 10.1c, using Verilog HDL. The output of the encoder was synthesized using Leonardo Spectrum. The synthesis results show that the critical path delay as well as the total number of gates is reduced when compared with the prevailing technology.

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Design and Analysis of Hybrid Operational Amplifiers Using Poly Si Thin Film Transistor For Low Voltage Applications[ ]


The design of Operational Amplifier in a new technique is presented in this paper, of a Hybrid Thin Film Transistor operational amplifier made by Poly Silicon thin film transistor and MOSFET which operates at 3V power supply. The Operational Amplifier designed is a two-stage Hybrid TFT OPAMP followed by an output buffer. This OPAMP employs a Miller capacitor and is compensated with a current buffer. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at high frequency. Optimization of one or more parameters may easily result into degradation of others while designing of two-stage op-amps. In this paper we analyze the results of Differential amplifier, Inverting amplifier, Non-Inverting amplifier, Integrator and Differentiator of hybrid operational amplifier, using HSPICE circuit simulator.

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FPGA Implementation of Low Power, High Speed, Area Efficient Invisible Image Watermarking Algorithm for Images[ ]


In recent years, the applications about multimedia have been developed rapidly. Due to rapid development in the network and communication field, it has become necessary to protect the data during transmission. Digital watermarking is a solution to the copyright protection and authentication of data in the network. Protection of digital multimedia content has become an increasingly important issue for content owners and service providers. So there has been growing interest in developing effective techniques to discourage the unauthorized duplication of digital data In this technique, based Image robust watermarking technique for color and gray scale images was performed. The RGB image is converted to HSV and watermarked by using discrete wavelet transform. Watermarking embedded stage and extraction stage is designed using invisible watermarking algorithm. Here the host signal is an image and after embedding the secret data a watermarked image is obtained and then extracts secret image and original image separately. Checking the watermark insertion and quality analysis various parameters like PSNR, Cross correlation etc FPGA implementation of invisible watermarking algorithm using the proposed design can operate at a maximum frequency of 344 MHz .An improvement of 28% in speed has been achieved by consuming considerably less number of resources of Vertex 6 6vsx315tff1156-2 FPGA device to provide cost effective solutions for real time image processing applications.

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VLSI-Implementation of Digital Keying Techniques Using VHDL[ ]


VHDL implementation of digital keying techniques is presented here. The blocks needed for generating binary amplitude shift keying (BASK), binary frequency shift keying (BFSK) and binary phase shift keying (BPSK) were designed, coded and simulated. A programmable read only memory (PROM) is also designed to store binary data. The blocks were coded in VHDL language and simulated using ModelSim tool. The proposed designs are focused at an academic objective of a course in digital communication.

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Design and Characterization of ECC IP core using Improved Hamming Code[ ]


Hamming code with additional parity bit can be used for single error correction and double error detection. In conventional hamming code redundancy bits are interspersed in powers-of-two positions at the transmitter end. At the receiver these redundancy bits are to be extracted from the powers-of-two positions. In improved hamming code the redundancy bits are placed at the end of data bits. This eliminates the overhead of interspersing redundancy bits at the sender end and their removal later at the receiver end. Further the overhead bits involved in the process of calculation of redundancy bits is lower in improved hamming code. This paper describes the design of a synthesizable Error Correction Codes (ECC) IP core which uses improved hamming code. The design is described using Verilog HDL, simulated using ModelSim and prototyped in Altera platform FPGA. Resource utilization and power analysis was done using Altera Quartus II. Hardware test results are obtained from Signal Tap Logic Analyzer. To make a comparison between ECC using conventional hamming code and ECC using improved hamming code Matlab plots are used.

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RTL Power Estimation for Large Designs[ ]


The increasing demand for portable electronic devices has led to emphasis on power consumption within the semiconductor industry. As a result, chip designers are now forced to consider the impact of not only speed and area, but also power throughout the entire design process. Power reduction has to be addressed at every design level, like system, RTL, gate and transistor-level where most power can be saved at the highest level. Good power estimation is essential for successful low power design. In order to evaluate how well a particular design type meets power constraints, designers have to often rely on CAD tools for power estimation. While tools have long existed for analyzing power consumption at the lower levels of abstraction like gate level and circuit level (PowerMill and SPICE) only recently tools with high-level power estimation capability are being developed. While system-level power estimation is new, power estimation from RTL-level and down have had many years to develop and mature. The RTL-power estimation can be divided into statistical- and simulation-based estimation. This paper surveys the various methods in high level power esimation, addressing techniques that operate at the RT Level of abstraction.

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Statistical Analysis of Signal Integrity Issues in CNT Interconnects due to Contact Resistance Variations[ ]


Carbon nanotubes have recently been proposed as a possible replacement of metal interconnects in future technologies. These interconnects are supposed to carry signal frequencies above 20GHz by the year 2020. Hence signal integrity analysis is inevitable under real life process conditions. Contact resistance of CNT interconnects are reported to be varying between 0K? to 120K?. However, no study has been extensively analysed its effect on signal integrity issues for these interconnects. This work aims to fill that gap by Statistical analysis of the impact of contact resistance variations on signal integrity issues of bundles of SWCNTs. This work revealed that the signal integrity issues due to contact resistance variations are more severely effecting signal timing variations than the crosstalk induced signal overshoots and undershoots.

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10 bit Delta Sigma D/A Converter with Increased S/N ratio Using Compact Adder Circuits[ ]


Data converters, ADCs and DACs, interface the real world of analog signals to the digital domain. They can be classified as ‘Nyquist rate converters’ and ‘Over sampled converters’. Former operates at a sampling rate of twice the input signal frequency. They do not make use of the advantages of exceptional high speeds achieved in the current VLSI technology. Also the limitations in matching accuracy of the analog circuits needed in this type, limits their accuracy to an effective number of bits (ENOB) of 12 to 14 bits for various implementations. Over sampling data converters uses sampling rate much higher than Nyquist rate, typically higher by a factor between 8 and 512 or higher. They can achieve over 20 ENOB resolution at reasonably high conversion speeds. The engine behind this over sampling converter is a delta-sigma modulator. The main advantage of delta sigma modulator is that they offer a very good separation of input signal from the quantisation noise due to the over sampling process and noise shaping. The Signal to noise ratio (SNR) for a Nyquist rate converter depends on the number of bits of the converter. In this type SNR can be increased by approximately 6dB per bit. In over sampling converters the SNR depends on the depth of oversampling also, which is specified as ‘Oversampling ratio’ (OSR). Theoretically, for each doubling in sampling rate SNR can be be improved by a factor of 3dB, , which corresponds to a half bit increment in Nyquist rate converters. Thus without increasing chip area SNR is increased. In this paper a 10 bit delta sigma DAC is implemented and SNR was measured with various sinusoids at different over sampling ratios. To reduce the number of transistors in the implementation, ‘Minimal energy dual bit adder (MEDB adder) is used.

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Modelling of On Current In a Scaled MOSFET Considering the Effect of Saturation Velocity and Temperature[ ]


The metal oxide semiconductor field effect transistor is the building block of VLSI(Very Large Scale Industry).Minimum featrure size of the ICs has shurnk consideably over the time of several decades. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area.As a consequence,the number of transistor has increased over time. When gatelength is scaled into nanoscale , second order effects are becoming a dominant issue to be dealt with in transistor design. In fact, over the past 30 years the number of transistors per chip has been doubled every 2-3 years once a new technology node is introduced. Accurate description of temperature effects in a device is necessary for a circuit level MOSFET model to predict circuit behaviours over a range of temperature. This paper analysis the limiting effects of saturation velocity on drain current and scaling of the on-current temperature effects in MOSFET devices.It is concluded that temperature dependence decreases with technology scaling.

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Comparison of FPGA Based Cordic Architectures [ ]


The COordinate Rotational DIgital Computer (CORDIC) algorithm is an iterative method for performing basic arithmetic operations including certain linear, trigonometric, hyperbolic and logarithmic functions. [1]-[3]. The algorithm only uses elementary shift-and-add steps to performing two-dimensional (2-D) plane vector rotations facilitating easy hardware implementation. This is mainly used in signal processing architecture. This paper presents a comparison of the various CORDIC architectures, especially in three different major styles iterative, parallel and pipelined structures with respect to their speed, area, and data throughput performance All three designs were coded in VHDL, simulated using Modelsim 6.2 c and Implemented in Xilinx Sparten 3E and NET FPGA and Synopsis ASIC synthesis tools.

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Design and Analysis of Power and Area Efficient 2/3 Prescaler Using E TSPC Logic[ ]


One of the important functional blocks in frequency synthesizers is the high speed dual modulus prescaler. The bottleneck of the dual modulus prescaler design is that it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) usually consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. In general, a divide-by-N/N+1 counter consist of flip flops and some extra logic implemented using logic gates which determine the terminal count. Here an E-TSPC logic based divide-by-2/3 prescaler suitable for low supply voltage (0.9V) and low power applications is been designed and implemented wherein the counting logic and the mode selection control are implemented using a single transistor. Thus the critical path is reduced which in turn enhances its working frequency. Simulation results show that, compared with the conventional TSPC and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler which incorporates the proposed 2/3 prescaler are designed and implemented. Simulation results show that the power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs. All prescalers were designed using the same 0.18µm TSMC CMOS process technology and simulated using Mentor Graphics ELDO.

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PULSE TRIGGERED FLIP FLOP DESIGN WITH CONDITIONAL PULSE ENHANCEMENT[ ]


A low-power pulse-triggered flip-flop (FF) design is proposed here. Here a two input pass transistor logic (PTL) based AND gate design is used to reduce the circuit complexity. In order to speed up the discharge along the critical path a conditional pulse-enhancement technique is implemented as and when needed. As a result, size of transistors in delay inverter and pulse-generation circuit can be reduced which result in power saving. In this paper comparison of various implicit and explicit P-FF are mentioned. This paper, describes a low-power implicit-type P-FF featuring a conditional pulse-enhancement scheme. Additional transistors are employed to support this feature. In spite of a slight increase in total transistor count, transistors of the pulse generation logic benefit from significant size reductions and the overall layout area is even slightly reduced. Various simulation results based on Complementary MOS (CMOS) 180-nm technology reveal that the proposed design features the best power and power delay product(PDP) performance than other FF designs under comparison. The introduction of clock gating concept into the proposed P-FF design increases its performance.

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Design of Complex Inter Connection Matrix Using Advanced Bus Architecture[ ]


The Advanced Microcontroller Bus Architecture (AMBA) is widely used interconnection standard for System on chip (SOC). Advanced High performance Bus (AHB) is a new generation of AMBA bus, which is intended to address the requirements of high -performance synthesizable designs.Multilayer AHB is an interconnection scheme,based on the AHB protocol that enables parallel access path between the multiple masters and slaves ina system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth and more flexible system architecture.In This paper we used HDL (Hardware Description Language) for designing the RTL (Register Transfer Level) code.Synthesis and simulation is done using Xilinx and Modelsim

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CAN Bus Protocol based Greenhouse System [ ]


In this paper, an Automatic Greenhouse Monitoring and Control system based on CAN Bus protocol and Mobile Web Server has been designed. The Intelligent Node in the Greenhouse measures the parameters inside it and the resulting data is monitored continuously. Any fluctuations from the set data would automatically start the control section functioning and thus, the required levels of the parameters are achieved.

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Timing Controller using FPGA MicroBlaze for a Digital Radar Receiver [ ]


With the popular hardware description languages in place, there is a wide range of options that enables Field Programmable Gate Array (FPGA) designers to design optimized hardware implementation adding to the flexibility that language-based design provides the designers. Designers get to implement flexible Intellectual Property (IP) core which is widely used for custom applications. Configurable soft processor cores that can be synthesized onto their FPGA products thus enhancing configurability and programmability are being manufactured by different vendors to suit the needs of front end users. The FPGA embedded processors use general-purpose FPGA logic to construct internal memory, processor buses, internal and external peripherals. This paper focuses on the design of a timing control and signal generation controller on Xilinx MicroBlaze for a digital radar receiver. MicroBlaze enhances critical timing algorithms important for radar communications with adequate advantages such as customization, flexibility, hardware acceleration, obsolescence mitigation and programmability with scalability. The processor environment in the FPGA fabric is utilized for providing customization of the timing unit for signal transmission. With the selection of an appropriate FPGA family, optimized hardware with high DMIPS benchmarks can be availed.

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Remotely Operated Submersible [ ]


This paper contains a brief description about the design of a Remotely Operated Submersible. ROS is a tethered submersible, controlled by a pilot located on land or from a boat or ship in the water. An umbilical tether containing a group of cables carry electrical power, video and data signals back and forth between the operator and ROS. Remotely Operated Submersible has manouvarability in Forward, Port, and Starboard directions by maintaining a constant heading. It can rotate in clock-wise and anticlockwise directions along its vertical axis. It can also dive underwater and hover at a particular depth.It is basically designed for underwater exploration.The paper addresses the basic system architecture and other design parameters in brief

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A Novel Printed Antenna for WLAN Applications at 2.45GHz[ ]


A novel single band microstrip antenna geometry for WLAN application is presented. A symmetrical antenna with its centre frequency at 2.45GHz is proposed. The proposed antenna is fabricated and the experimental results are reported. Important characteristics of the proposed antenna, such as radiation pattern, return loss, bandwidth, and efficiency have been investigated.

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Low Cost Fault Diagnostics System for Vehicles[ ]


On-board diagnostics, or OBD, is an automotive term which refers to a vehicle's self-diagnostic and reporting capability. These systems give the vehicle owner or a repair technician access to state of health information for various vehicle sub-systems. The amount of information available via OBD has varied widely since its introduction in the early 1980s. Early instances of OBD would simply illuminate a malfunction indicator light, or MIL, if a problem was detected but would not provide any information about the nature of problem. This project proposes the development of vehicle diagnostics system based on low cost microcontrollers which can provide real-time readings of vehicle subsystems, which allow one to rapidly identify and remedy malfunctions within the vehicle. The proposed system has a microcontroller based processing system which consists of transducers installed at different parts of vehicle for observation of various parameters, microcontroller unit for processing the output of sensors and signal conditioners, calculate the real- time values of vehicle parameters and give output to display systems. The system will be able to diagnose faults in parameters, abnormal abrupt changes and notify user of any abnormal condition. The system is basically intended for vehicles that do not have built-in OBD systems. It is a user friendly system with LCD display, MIL, GSM and Keypad interfacethroughwhichusercanviewparameter values, warning notifications and defines custom limits for different parameters according to vehicle.

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Low Cost Offline Route Learning System[ ]


A low cost portable device consisting accelerometer, digital compass, Real time clock, microcontroller and flash memory records the route travelled by a vehicle. This is offline device used to keep the path recorded, so that we can retrieve it to know the route between two points. The path can be retraced by excel software which is much common. This can be considered as an alternative for costly GPS systems. It records the movement of person in two dimensions and path is retraced using Microsoft excel software. The accelerometer gives acceleration details and digital compass gives direction details. The device is based on commercially available sensors.

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MEMS Based C Band Tunable 16 Array Vertical Cavity Surface Emitting Laser[ ]


This paper elaborates a C-Band Tunable MEMS 16-array Vertical Cavity Surface Emitting Laser (VCSEL), which is suitable for wide use in WDM applications. Optical detectors, optical filters and Wavelength-tunable lasers play a pivotal role in the future ultrahigh bandwidth dense-wavelength-division-multiplexed (DWDM) optical network, enabling emerging innovative applications such as wavelength-on-demand in a reconfigurable all-optical network. VCSEL is the key optical source in optical communications. The advantages of VCSEL include simpler fiber coupling, easier packaging and testing, ability to be fabricated in arrays at low cost. The VCSEL array was made tunable in C-Band (1520-1550nm) by varying the length of the Fabry Perot cavity. The Fabry Perot cavity length is varied by using fixed-fixed beam electrostatic actuation. The VCSEL array is designed on to a single wafer using Intellisuite software and the optical analysis is done by using MATLAB.

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Design of CPW fed Monopole Slot Antenna for WiMAX Applications[ ]


In this paper, a CPW fed monopole slot antenna is proposed. A rectangular patch embedded to slot antenna is designed on 50x30mm2 RT Duroid substrate with thickness 3.175 and relative permittivity 2.33. The antenna operates at a resonant frequency of 3.5GHz. The maximum gain obtained by proposed antenna is 3.41dBi. The radiation efficiency of antenna is as high as 99.65%. The proposed antenna structure is simulated using Advanced Design System (ADS) software. The acceptable radiation characteristics and obtained results such as return loss, gain, efficiency shows that the designed antenna is well suited for WiMAX application.

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Performance of OFDM Systems Using Nonlinear Companding Transform[ ]


Orthogonal Frequency Division Multiplexing (OFDM) is an efficient method of data transmission for high speed communication sys-tems. The main drawback of OFDM system is the high Peak to Average Power Ratio (PAPR) of the transmitted signals, which reduces the efficiency of transmit high power amplifier. PAPR is one of the serious problems in any wireless communication system using multi carrier modulation technique like OFDM. Coding, phase rotation, clipping etc. are among many PAPR reduction schemes that have been proposed to overcome this problem. In this paper, a novel scheme is proposed for PAPR reduction. The key idea is to transform the original Gaussian-distributed OFDM signals into a specific statistics form. Significant reduction in PAPR has been achieved using this technique and this enables more flexibility in the companding form. A favorable tradeoff between PAPR reduction and BER performance can be achieved by properly choosing the transform parameters. The significance and accuracy of the analytical expressions for transform gain in PAPR, complementary cumulative density function (CCDF), and selection of transform parameters are justified by the simulation results.

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Compact Ultra wideband Log Periodic Dipole Antenna with WLAN Rejection by using U shape Ground Structure[ ]


In this paper, compact Log-periodic dipole antenna with single band notched characteristics is presented by introducing different ground structure (DGS). The proposed antenna consists of U-shape ground structure that produces WLAN band-notched rejection characteristics from 5.1 GHz to 5.9 GHz and size of the antenna is reduced to improve the compactness. This band notch is proposed for Ultra wideband applications. The Voltage Standing Wave Ratio (VSWR) is less than 2 between 3.1 GHz to 10.6 GHz. The proposed antenna with WLAN rejection frequency notch is designed, fabricated.

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Prediction of Resonant Frequencies of Rectangular Circular and Triangular Microstrip Antennas using a Generalized RBF Neural Model [ ]


Microstrip antennas have proved to be the excellent radiators for many applications. It is so because of their numerous advantages such as light weight, low profile, conformable to planar and non-planar surface, low fabrication cost because of printed-circuit technology, integrability with other microwave integrated circuits (MICs) on the same substrate etc. Because of inherent characteristic of microstrip antennas to operate in the vicinity of resonant frequency, this resonant frequency needs to be calculated accurately. This paper presents a simple, accurate and fast approach based on radial basis function (RBF) neural networks for predicting the resonant frequencies of rectangular, circular and triangular microstrip antennas, simultaneously. The computed results are in very good agreement with their measured counterparts.

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MSA fed Circularly Polarized High Gain Antenna [ ]


A microstrip antenna fed circularly polarized high gain antenna is proposed. The suspended microstrip antenna is fabricated on FR4 substrate and placed at 1mm from ground. Circular polarization is obtained by diagonal feeding of microstrip antenna and using two shorting pins. This MSA feeds 3 X 3 array of square parasitic patches fabricated on a low cost 1.6 mm FR4 dielectric layer. The dielectric superstrate layer is suspended in air at ?o/2. The printed MSA is fed by a 50 O coaxial probe. The VSWR is < 2 and axial ratio < 3 over 5.725 - 5.875 GHz, ISM frequency band. The antenna provides 13.5 dB gain with gain variation of < 1.0 dB over 5.725-5.875 GHz. The antenna structure also provides more than 70 % efficiency, SLL < -18 dB and front to back lobe ratio of more than 22 dB.

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Printed MSA fed High Gain Wide band Antenna using Fabry Perot Cavity Resonator[ ]


A low cost, printed high gain and wideband antenna using Fabry Perot cavity resonator for wireless applications is proposed. The antenna structure consists of a suspended microstrip antenna fabricated on FR4 substrate and placed at 1 mm from ground. MSA feeds 4 X 4 array of square parasitic patches fabricated on 1.6 mm thick FR4 dielectric layer. This superstrate layer is suspended in air at ?o/2. Closely spaced square patches with less than 0.1? x 0.1? are fabricated near MSA to provide an inductive surface and to reduce gain variation. The VSWR of proposed antenna is < 2 over 5.725 - 6.4 GHz frequency band. The antenna provides 16.0 dB gain with less than 2.5 dB gain variation over 5.725-6.4 GHz, covering WLAN band and uplink C-band for satellite communication. There is small but acceptable radiation pattern variation over the 5.725-6.4 GHz band. The antenna structure also offer < -16 dB SLL and cross polarization with more than 20 dB front to back lobe ratio. The proposed structure is suitable for terrestrial and satellite communication.

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Multilayer Printed MSA fed High Gain Antenna[ ]


A multilayer printed microstrip antenna fed high gain antenna using array of parasitic patches on a FR4 superstrate layer is proposed. The suspended microstrip antenna is fabricated on FR4 substrate and placed at 1mm from ground. This suspended MSA feeds 5 X 5 array of square parasitic patches which are fabricated on a 1.6mm thick FR4 layer. This layer is suspended in air at ?o/2. The printed MSA is fed by a 50 O coaxial probe. The antenna provides 17.8 dB gain with gain variation of < 1.5 dB over 5.725-5.875 GHz. The antenna structure also provides more than 80 % efficiency, SLL < -18 dB and front to back lobe ratio > 22 dB. The VSWR is less than 2 over 5.725 - 5.875 GHz, frequency band. The proposed structure can be used for terrestrial and satellite communications.

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Optimization of an Efficient Routing Protocol in Mobile Ad Hoc Networks[ ]


In mobile ad-hoc network (MANET), a host may exhaust its power or move away without giving any notice to its intermediate nodes. It causes changes in network topology, and thus, it significantly degrades the performance of a routing protocol. Several routing protocol studies are based on node quality and find node minimum distance path. In an estimated distance (EstD)-based routing(EDRP) protocol to steer a route path in the general direction of a destination, it can restrict the propagation range of route request (RREQ) and reduce the routing overhead. The EstD is a combination of EGD and ETD protocol. In the protocol, every node evaluates the link quality through the process of the EGD to eliminate the weak links and then uses the EstD to steer the RREQ packets. We proposed we implement the optimized Link State Routing Protocol for to dissemination of data over the nodes in mobile ad-hoc networks. In simulation results show that the proposed protocol significantly reduced routing overhead, improve the routing performance and reduce the time delay.

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Reduction of Positioning Error in Wireles OFDM Based Cellular Networks[ ]


Localization of a mobile station (MS) in a cellular network is performed using multicarrier transmission for orthogonal frequency division multiplexing (OFDM)-based cellular networks. In this paper, we propose a multicarrier (MC)-based positioning system for Orthogonal Frequency Division Multiplexing (OFDM)-based cellular networks such as WiMAX or future 4G system together with a novel localization protocol that is optimized for this system A positioning system is proposed where the relative positioning and interference suppression is reduced compared to the previous methods. A localization protocol is defined in which four positioning methods are analyzed. For achieving this Cramer-Rao Lower Bound (CRLB) is implemented and the paper demonstrates the enhanced performance of Best linear unbiased estimator (BLUE) based algorithms to implement the proposed methods when location a mobile station using cellular base stations

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Multicarrier CDMA with OFDM for Data Centric Applications and Performance Analysis [ ]


In 4G wireless communication systems, Multicarrier Code Division Multiple Access (MC-CDMA) is one suitable choice to achieve high data rate. MC-CDMA is the combination of CDMA and OFDM schemes, resulting in to getting the advantage of both the schemes. In this paper the BER performance analysis of MC-CDMA using different spreading codes, modulation techniques, channel models, with and without receiver diversities are carried out. Hence achieving increased BER performance and thereby increasing the total capacity by mitigating the effect of Multipath Interference (MI) and Multiple Access Interference (MAI) within MC-CDMA systems.

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A Review on Distributed and Centralized Protocols in Wireless Sensor Networks[ ]


Wireless sensor networks (WSNs) are a network of many typically small sensor nodes. These WSN have huge application in habitat monitoring, disaster management, security and military, etc in locations which are restricted or inaccessible to human users. Wireless sensor nodes are very small in size and have limited processing capability with very low battery power. This restriction of low battery power makes the sensor network prone to failure. Protocols which are Power aware, support Data aggregation, has distributed mechanism for constructing topologies may be effective technique in this context . In this paper an attempt is made to review four protocols (LEACH, PEGASIS, PEDAP and L-PEDAP) in WSN with discussion on their variants

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An Autonomous System to Detect Multiple Attacks in Manet[ ]


The dynamic and cooperative nature of ad-hoc networking without a centralized authority for authentication and monitoring is susceptible to attacks that breaks down or exploits the co-operative behavior of the ad-hoc routing. Routing attack and Byzantine attack will leads to the most devastating damage to the MANET. This paper dealing with an autonomous system to detect both Routing and Byzantine attacks in MANETs and preventing its subequent actions against the security threads. Here the intrusion detection is based on Node Authentication message (NAM) Algorithm and Intrusion Identification Message (IIM) Algorithm, which are based on end to end communication between the source and the destination. And then prevents its subsequent action against the security threads by using Adaptive time wise isolation mechanism. This temporary isolation procedure will consider both the attacks and the risk caused by its counter measures. It is based on Extended Dempster Shafer theory of evidence with a notion of important factors. Since this approach considered the potential damages of both the attack and counter measures the proposed method is an effective approach compared with the existing binary and naive fuzzy response decisions.

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Secured Broadband Data Access System In Wi MAX[ ]


Security mechanism is to meet the expectations from mobile users to provide seamless services in mobile WiMAX. Handover should take place in highly secured and in most improved means. The main motive of the mobile technologies is to provide seamless cost effective mobility. But this is affected by Authentication cost and handover delay since on each handoff the Mobile Station (MS) has to undergo all steps of authentication. To overcome these vulnerability we propose an Enhanced EAP-based pre-authentication for fast and secure inter-ASN handovers (HO) using WPKI (wireless public key infrastructure). In this approach, a improved X.509 certificate is generated based on Elliptical Curve Cryptography (ECC) algorithm, then an enhanced mutual authentication flow, which enhances the security and working efficiency of the mutual authentication in multi-hop WiMax system is designed. Asymmetric key cryptography is used to secure the pre-authentication message exchange with low demand of computational resource. The proposed scheme can also meet the security requirements of an authentication protocol. The proposed scheme increases the security and practicability of WiMax system, which has better referenced value to the improvement of IEEE 802.16e standards. The proposed work is simulated by NS2 model and by MATLAB.

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Image Resolution Enhancement using Multi Resolution Wavelet Transformations[ ]


In this paper an image resolution enhancement technique for Additive White Gaussian Noise (AWGN) removal is verified aiming high resolution image output. In image resolution enhancement, the main loss is on its high frequency components (i.e., edges), which is due to the smoothing caused by interpolation. In order to increase the quality of the super resolved image, preserving the edges is essential. In this work, Discrete Wavelet Transform (DWT) has been employed in order to preserve the high frequency components of the image. Along with DWT, un-decimated wavelets transform, Stationary Wavelet Transform (SWT) for image decomposition and restoration. For signal mixing techniques like bilinear and bicubic interpolation were adopted. In the process, the modified noise minimized high frequency sub bands of DWT and SWT are interpolated with the average band of the image. The resultant image then made to undergo inverse DWT for restoration of denoised image. The proposed method is verified with MATLAB simulations and the experimental results confirms high resolution of image and been verified with Peak Signal to Noise Ratio (PSNR). The proposed method is superior with PSNR when compared with other state of the art methods.

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Detection of Fingerprint Alteration Using Scars Minutiae Density and Ridge Discontinuity[ ]


A novel method for detecting altered fingerprints using scars, minutiae density and ridge discontinuity is proposed here.This paper mainly focuses on FFT enhancement for ridge discontinuity analysis and use of scars along with ridge discontinuity and minutiae density for alteration detection. The scar is detected by adaptive average filtering and thresholding. This method is found suitable for the detection of all types of alteration viz. obliteration, distortion and imitation.

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Face Detection & Smiling Face Identification Using Adaboost & Neural Network Classifier[ ]


Face detection in images is a computer technology that examines the problem of detecting the locations in arbitrary (digital) images where faces are present. In other words, given a single image, the goal is to determine whether or not there are any faces in the scene and, if present, return the specific location and fit each face into the bounding box defined by the image coordinates of the corners. Smile detection in face images is an interesting problem in many applications. Here we present an efficient approach to face detection and corresponding smiling face identification using Adaboost and Neural network classifier

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Brain MR Image Segmentation using Enriched FCM[ ]


Medical image segmentation has been an area of interest to researchers for quite a long time. Segmentation of brain MRI is very complex. Standard Fuzzy C Means (FCM) algorithm has been widely used for brain image segmentation. But this standard FCM doesn’t take into account the spatial information. An improved version of standard FCM is presented which takes into account information about neighboring pixels also. This new method has many advantages both in terms of computational efficiency and computational time

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A Novel Patch Based Denoising Scheme [ ]


This paper proposes a denoising scheme which aims at removal of white gaussian noise present in the image. The framework works in spatial domain. We propose a patch-based filter that exploits patch redundancy for image denoising.The system checks for the presence of white gaussian noise in the input image. In the absence of white gaussian noise, it does not undergo denoising scheme. In such case, the image will be displayed as such. If the image contains white gaussian noise, then the framework uses both geometrically and photometricaly similar patches to estimate the different filter parameters. In order to group geometrically similar patches, Fuzzy C-means clustering is employed. Then the implementation uses the estimated parameters to denoise patch wise.

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Real Time Miniaturized ECG System With Bluetooth Transmission[ ]


There is the need to consider miniaturized ECG devices for proper and effective way of recording and analyzing ECG signals from the human body.The world’s ageing population and prevalence of chronic cardiovascular diseases have led to high demand of simply,portable,cost effective and accurate ECG devices.A small portable ECG amplifier system is presented using microcontroller to analyze the ECG signals and Bluetooth to interface these signals to the PC.The aim of this project is to design and fabricate a portable ECG amplifier system which utilizes microcontroller and bluetooth to analyze abnormal ECG signals.This device detects some abnormalities of the heart such as bradycardia and tachycardia.The device has three leads and these leads are attached to the users or patients to get the ECG signals.LED and Buzzer are incomperated in the system to detect the state of the QRS complex at every ECG cycle.The experimental results show that it is possible to get these signals on the PC using microcontroller and the Bluetooth which is cost effective,user friendly,and easy to carry around

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A Practical Approach of Self Tuning Fuzzy Logic Controller for Water Bath System Applications [ ]


This project is based on the self-tuning fuzzy logic controller consciously for temperature process , the performance of the system should be trustable. The water bath system system combines the advantages of Self Tuning and Fuzzy Logic Control schemes. In order to assess the performance of the suggested control system methods, upshots from simulation of the process are mounted.

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Fuzzy Entropy Based MR Image Segmentation Using Particle Swarm Optimization [ ]


An image segmentation technique based on fuzzy entropy is applied for MR brain images to detect a brain tumor is presented in this paper. The proposed method performs image segmentation based on adaptive thresholding of the input MR images. The image is classified into two membership functions, whose member functions of the fuzzy region are Z-function and S-function. The optimal parameters of these membership functions are determined using Particle Swarm Optimization algorithm by maximizing the fuzzy entropy. Through a number of examples, the performance is compared with those using existing entropy-based object segmentation approaches and the superiority of the proposed method is demonstrated. The experimental results are compared with the exhaustive method and Otsu segmentation technique; the results show the proposed fuzzy entropy method integrated with PSO achieves maximum entropy with proper segmentation of infected areas and with minimum computational time

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OPTIMIZATION OF VARIOUS SPECIFIC AND GENERIC STEGANALYSIS SCHEMES[ ]


The objective of steganalysis is to detect messages hidden in cover objects, such as digital images, video and audio. The ultimate goal is to extract and decipher the secret message. In a few recent cases, images are used as carrier medium by some unauthorized users as it is less suspected for criminal purposes. There are two types of image steganalysis techniques referred as Specific and Generic steganalysis schemes. The Specific approach represents a class of image steganalysis techniques that very much depend on the underlying steganographic algorithm used and have a high success rate for detecting the presence of the secret message if the message is hidden with the algorithm for which the techniques are meant for. The Generic approach represents a class of image steganalysis techniques that are independent of the underlying steganography algorithm used to hide the message and produces good results for detecting the presence of a secrete message hidden using new and/or unconventional steganographic algorithms. Various steganalysis techniques are implemented and analyzed to find out the most efficient one.

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MEMS Based Trajectory Recognition and Human Computer Interaction for the Disabled People[ ]


The growth of miniaturization technologies in electronic circuits and components has greatly decreased the dimension and weight of consumer electronic products, such as smart phones and handheld computers, and thus made them more handy and convenient. Within the last decade, many improvements have been made in the performance of gesture and speech recognizers and current technology is discussed in relation to the needs of the disabled population. This paper presents an accelerometer-based device for gesture recognition and speech recognition system for the disabled people. The speech recognition system is attached to the device .By changing the position of MEMS (Micro Electro Mechanical Systems) users are able to show the characters’ in the PC and the user speech commands can be interpreted by the computer. The acceleration signals measured from the accelerometer are transmitted to a computer via the wireless module.

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