temperature) circuit which includes the other group of transis
tors, a fixed DC voltage which doesn’t change with tem- perature is generated. This voltage is typically 1.26 volts, which is approximately the band gap of silicon. [2][3]
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Design of Bandgap Reference Circuit for Driving
Resistance Load with Low Impedance
Hamid Moharrami, Ziaeddin Daie Koozekanani, Khadijeh Karamzadeh, Fateme Moharrami
2.5V and 6V and between 0C and 100C. It has a PSRR of 41dB under normal operating conditions. This circuit works in a current feedback mode, and it generates its own reference current, resulting in a stable operation. A startup circuit is required for successful operation of the system. Varia- tion of the reference voltage with RL from 40_ to 200_ at 27°C_is 4mV.
(BGR), Temperature Coefficient (TC).
—————————— ——————————
Many analog circuits require voltage references, such as A/D and D/A converters. A voltage reference must be, inherently, well-defined and insensitive to temperature, power supply and load variations. The resolution of an A/D or D/A con- verter is limited by the precision of its reference voltage over the circuit’s supply voltage and operating temperature ranges. The bandgap voltage reference is required to exhibit both high power supply rejection and low temperature coefficient, and is probably the most popular high performance voltage refer- ence used in integrated circuits today.
By definition a bandgap reference is a voltage reference of which the output voltage is referred to the bandgap energy of the used semiconductor. The first bandgap reference was pro- posed by Robert Widlar in 1971 [1].
The working principle of a bandgap voltage reference can be illustrated by Fig1. Since VBE decreases approximately linear with temperature while VT increases linearly with tem- perature, a low-temperature-dependence VREF can be ob- tained by scaling up VT and summing it with VBE.
As a well-established reference generator technique, bandgap reference is most popular for both Bipolar and CMOS technologies. The principle of the bandgap circuits re- lies on two groups of diode-connected BJT transistors .
running at different emitter current densities. By canceling the negative temperature dependence of the PN junctions in one group of transistors with the positive temperature de- pendence from a PTAT (proportional-to-absolute-
————————————————
• Ziaeddin Daie Koozekanani, Electrical Dept.,Eng.Faculty, university of Ta-
briz, Tabriz,Iran, zdaie@tabrizu.ac.ir
• Khadijeh Karamzadeh, Electrical Dept. , Eng. Faculty, Islamic Azad Universi-
ty, Miyaneh Branch, Miyaneh, Iran, kh_karamzadeh_h@yahoo.com
• Fateme Moharrami, Electrical Dept. , Eng. Faculty, Islamic Azad University,
Tabriz Branch, Tabriz, Iran, f.moharrami1989@gmail.com
temperature) circuit which includes the other group of transis
tors, a fixed DC voltage which doesn’t change with tem- perature is generated. This voltage is typically 1.26 volts, which is approximately the band gap of silicon. [2][3]
Fig1.Concept of bandgap Voltage Reference
The outline of this paper is as follows: in section II circuit description is presented. Section III presents circuit analysis units. In the section V, we demonstrated simulation result. The results were obtained by simulation produce in a 0.35 µm pro- cess.
Adding two voltages that have temperature coefficients of opposite sign with suitable multiplication constants generates a reference voltage. The resulting voltage obtained is inde- pendent of temperature. The diode voltage drop across the base-emitter junction, VBE, of a Bipolar Junction Transistor (BJT) changes Complementary to Absolute Temperature (CTAT) [4]. Whereas if two BJTs operate with unequal current densities, then the difference in the base emitter voltages,
_VBE, of the transistors is found to be Proportional to Abso- lute Temperature (PTAT). The PTAT relationship is given by [5],
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∆VBE = VT ln m; VT = kT /q (1)
where, k is Boltzmann’s constant, T is the absolute temperature, q is the electron charge and m is the ratio of the current densities of the two BJTs. The PTAT voltage may be added to the CTAT voltage with suitable weighting constants to obtain a constant reference voltage. By using a supply inde- pendent current source, a current Iss is passed through BJT A. The same current Iss flows through m transistors connected in parallel, identical to A. Thus the current density of A is m times the current density of the m BJTs identical to A, connect- ed in parallel. The voltages at node X and Y are maintained at the same value, VBE using a feedback network through a dif-
maybe set. This arrangement provided an elegant arrange- ment to generate the reference voltage while conserving volt- age headroom. The circuit has a stable operating point at which no current to flows through it. An arrangement must be made to force the saturation when the supply is turned on. This function is carried out by the startup circuit.
The voltages X and Y are fixed by feedback; hence result the VREF is given by,
Vref = Iss .R2 + VBE (4)
∆VBE
ferential amplifier. This results in a voltage of ∆ VBE, across
the resistor R1. The voltages VBE and ∆ VBE are added to
obtain the reference voltage. The circuit also requires a startup
circuit since there exists a stable state at which no current
Vref =
R1
R2
.R2 + VBE
(5)
flows through the circuit. The startup circuit forces the transis- tors to turn on and the circuit to operate at its other stable state
Vref
= .VT .ln m + VBE
R1
(6)
to generate the reference voltage. It should be noted that an ideal BJT is not available in CMOS technology.
In the order achieve a zero temperature coefficient; the fol- lowing equation must be satisfied.
∂Vref
R2
∂VT
∂VBE
The bandgap reference voltage is generated by adding the base emitter voltage, VBE, of a BJT to the difference in base emitter voltage, ∆ VBE of BJTs with a ratio of current density m. In order to generate a stable circuit, it is necessary to keep the BJT in the exponential region.
= ln m. +
∂T R1 ∂T
∂Vref = 0
∂T
(7)
∂T
(8)
The change of the voltage of reference node is made possi-
R2 ln m. ∂VT
= − ∂VBE
(9)
ble by adding variable resistor in the base of Q1 and Q2 tran-
sistors. Ideally, the error amplifier has a high voltage gain A,
and therefore VX=VY can be achieved, when
VDSTP1=VDSTP2 can be easily obtained to provide a very good current matching by M1 and M2. VREF can be generated
by this structure without the need of an extra current branch.
Both power consumption and errors can be reduced effec- tively.
A pnp BJT is made using the n-well normally associated with a PFET [4], the p substrate behaving as the collector. The OPAMP provides the base voltage to the transistors which are connected as current mirrors. By selecting the value of R1 and current Iss, the circuit may be designed to operate at the de- sired operating point. The value of R1 is given by,
R1 = ∆VBE / ISS (2)
Since the same current Iss flows through R2, the voltage at the output reference voltage nodes is given by,
R1
R1 ∂T ∂T
Vref = VBE + ∆VBE .
2
(3)
Fig. 2: Schematic of Bandgap Reference Circuit showing the sup-
ply independent current source, generation of reference voltage
Thus by selecting the value of R2 the weighting constant
and driving low Impedance block
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The equation shows that R1, R2 and m affect on the TC of Vref. m is the ratio of the surface of Q1 and Q2 transistors. Because layouts on both BJTs and resistors should be well planned and designed so that consistent performance can be maintained with minimum need of trimming in mass produc- tions. Better matching can be achieved by a common-centroid layout [6],[7]. However a large value of N is not preferred as the separation of devices increases, and this will introduce more errors. Moreover, as shown in (8) there is no signification increase on the ln(m) function when m increases.
For the resistor layout, common-centroid layout should be also used to obtain better matching [7]. Polysilicon is a better material than diffusion since its tempco is low. An even better material is high-resistive polysilicon, since it has a negative tempco. We used in the simulation.
As mentioned above, the amplitude of R1 and m are set be- fore. Therefore only R2 is affected in the thermal characteristic.
The OPAMP was used to maintain equal node voltages and provide a feedback to maintain the drain currents constant and insensitive to supply variations. A high gain of the OPAMP would result in better voltage tracking of nodes X and Y (Fig2). The common mode voltages play an important role in determining the OPAMP topology. The input common mode was determined by the base emitter voltage of the BJT. In order to meet the input common mode condition an active current mirror circuit with a PMOS driver was selected.
The output common mode voltage corresponds to the gate voltage of the current mirror transistors. A second stage was added to the OPAMP to increase gain and shift the common mode voltage up by using an NMOS driver. The NMOS driver only provided an output common mode of about 0.4 V. By adding a diode-connected transistor to the second stage, the output voltage was pushed up to about 1.3 V without any ef- fect on the gain of the stage. The voltage drop across the diode connected transistor is about 1.2 V corresponding to VTH + VDSAT. The gain of each of the stages of the OPAMP is given by
A=gm.Ro (9)
Where, Av is the gain, gm is the transconductance of the driving transistor and RO is the effective output resistance at the output node.
Transistors TN1, TN2, TN3 and TP4 constitute the startup cir- cuit. Initially all the transistors start off in off state. The voltage at the gate of TN1 is low and so it remains in off state. TP4 being diode connected is always on and so the transistor TN2 turns on forcing the drain to a low value. The current mirror stack turns on and the gate voltage of TN1 rises and it starts to conduct. At this point there is a competition between the out- put of the amplifier TP6 and TN2 for the current source load. TN2 is designed to be a weak transistor so the amplifier takes control of the current mirror gate (Fig3).
When the bandgap voltage is high enough ( ~1V) the tran- sistor TN1 turns on. TN1 in linear region has to compete with TN2 in saturation so it is designed to be a big transistor. It draws all the current from TP2 and the base voltage of TN2 falls till it turns off. In this state the gate voltage at TN2 is about 0.6 V. This is high enough for the transistor TN1 to be conduct slightly. A diode connected transistor TN3 is added to increase the threshold voltage at the gate of TN3 to turn off. The transistor TP4 is designed to be a weak device so that low current flows through the parasitic path when the circuit is in full operation.
The Opamp_was used to maintain equal node voltages. A high gain of the OPAMP would result in better voltage track- ing of nodes. In fact, this opamp and M4 (Fig2) transistor pro- vide sufficient current for low Impedances without effecting over the main characteristic of bandgap reference
Fig. 3: Schematic of Bandgap core Circuit with startup
The bandgap reference voltage gives a voltage of 1.23V when adjusted to have a zero temperature coefficient at 27C. Fig4 shows the result of the simulation. As can be seen an overall temperature coefficient of 0.01mV/K is obtained between 0°C and 100°C. The response it worse for temperatures from 60-
100°C with a temperature coefficient of 0.024mV/K. Below these temperatures the temperature coefficient is 0.016mV/K.
Fig 5 shows variation of IL when temperature changes be- tween 0°C to 100°C. Temperature coefficient of 0.0005mA/K is obtained.
Fig 6 shows the variation when the supply voltage is var- ied from 2.5V to 6V. The relative variation is 0.41% at 27C.
Fig 7 shows the variation when the RL is varied from 40 Ω
to 200 Ω . The relative variation is 0.325%. at 27C.
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A bandgap reference with a current feedback mode has been designed to drive low Impedance. The circuit uses no external current sources and is designed to have a zero temperature coefficient at 27°C. The design is simulated with 0.35µm CMOS process. Table 1 shows the summary of performance of proposed circuit. The output voltage is 1.2364V at the nominal operating condition of 27°C temperature and 3.3V supply voltage. It has a temperature coefficient of 0.01mV/K from 0-
100°C.
Fig 6: Variation of the reference voltage with supply voltage at 27C
Fig 4: Variation of bandgap reference with temperature 
Fig 7: Variation of the reference voltage with RL at 27C
TABLE1: SUMMARY OF PERFORMANCE
Fig 5: Variation of current load with temperature at
Vdd=3.3v
REFERENCE
[1] Pease, Robert, “ The Design of Band-Gap Reference Circuits: Trials and
Tribulations”, IEEE 1990 Bipolar Circuits and Technology Meeting, pp
214- 218, 1990.
[2] Robert A. Pease, “The Design of Band-Gap Reference Circuits: Trials and Tribulations”, IEEE Proc. of the 1990 Bipolar Circuits and Technology Meeting, Minneapolis, Minnesota, Sept. 1990.
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 924
ISSN 2229-5518
[3] K. Lasanen, V. Koorkala, etc., “Design of A 1-V Low Power CMOS Bandgap Reference Based on Resistive Subdivision”, IEEE 2002.
[4] B. Razavi, “Design of Analog CMOS Integrated Circuits”, New york, NY: 2001, ch 11.
[5] D. Hilbiber, “A New Semicondictor Voltage Standard”, IEEE J. of
Solid-State Circuits, vol. 8, pp. 222-226, June 1973.
[6] K. Lasanen, et. Al, “ Design of a 1-V low power bandgap reference based on Resistive Subdivision”, Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma,USA, August 2002.
[7] D. John and K. Martin , “Analog Integrated Circuit Design”, Wiley
1997
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