Author & Title

Technology

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Moselund K.E., Bouvet D., Pott V., Meinen C., Kayal M., and Ionescu A.M., “Punch- through impact ionization

MOSFET (PI- MOS): From de- vice principle to applications,”[1]

TCAD

-

-

-

-

punch- through im- pact ioniza- tion

MOSFET

High Current Consumption

High temperature stability,

less switching activity

Hysteresis width can be optimized by the value of Vds.

Leung Wingyu, Hsu Fu-Chieh, and Jones Mark- Eric, “The Ideal SoC Memory: lT- SRAM,”[2]

CMOS

180

-

-

300

-

multi-bank architecture and multi- layer metal interconnect

high- frequency operation, short latency, transparent refresh and soft-error

rate

Easy to port, remove process incompatibility, extremely scal- able,

cost effective

1T-SRAM enables the economic embedding of very large quantities of memory in SoC designs.

Jin Niu, Chung Sung-Yong, Yu Ronghua, Heyns Roux M , Berge Paul R., and Thompson Phillip E., “The Effect of Spacer Thickness- es on Si-Based Resonant Inter- band Tunneling Diode Perfor- mance and Their Application to Low-Power Tun- neling Diode SRAM Cir- cuits,”[3]

N channel depletion mode FET

-

-

-

0.5

Si based res- onant inter- band tunnel- ing diodes (RITD)

Temperature change may effect

Low stand by power con- sumption, in- crease circuit speed,

reduce com- ponent count,

Suitable for low power memory ap- plications, Spacer thick- ness reduced to 16nm, Current den- sity reduced to 0.5A/cm2, peak-to-

valley current ratio (PVCR) reduced to 2.2

Glaskowsky Peter N., “MoSys Ex- plains 1T-SRAM Technology

Unique Architec- ture Hides Refresh Makes DRAM Work Like SRAM,”[4]

CMOS

-

-

-

-

Hide refresh technique- DRAM work like SRAM

Area may increase

High speed , high density,

No refreshing is required,

No wait state,

Jones Mark-Eric, “1T-SRAM-Q™: Quad-Density Technology Reins in Spiraling Memory Re- quirements,”[5]

45

CMOS

-

-

-

-

Quad Densi- ty Technolo- gy

Complex designing

Highly scala- ble,

Reliable, Small size,

Cost effective, Enhanced soft error rate, Improved yield

4times higher density than traditional 6T SRAM, Enhanced reliability using Trans- parent error

correction

Author & Title

Technology

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Somasekhar Dinesh, Ye Yibin, Aseron Paolo, Lu Shih-Lien, Khel- lah Muhammad, Howard Jason, Ruhl Greg, Kar- nik Tanay, Borkar Shekhar Y., De Vivek, and Keshavarzi Ali, “2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a

65nm Logic Pro- cess,”[6]

65

-

0.00028000

2000

1.1

Pipelined macro cells

area may increase

Fast cycle time,

Faster read

operation

retention time =10µs, Array Den- sity

92Mbit/cm2

Meinerzhagen Pascal, Teman Adam, Mor- dakhay Anatoli, Burg Andreas, and Fish Alexan- der, “A Sub-VT

2T Gain-Cell Memory for Bi- omedical Appli- cations,”[7]

180

-

-

-

0.4(sub- Vt)

SUB-VT GAIN-CELL

Capacitive coupling may occur

Good energy efficiency,

low power consumption, highly robust

data reten- tion time is higher than data access time

Author& Title

Technology

(nm)

Power

(µW)

Area

(mm2)

Freq (MH z)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Ramesh Ani- sha, Park Si- Young, and Berge Paul R., “90 nm 32x32 bit Tunneling SRAM

Memory Ar- ray With 0.5 ns Write Ac- cess Time, 1 ns Read Ac- cess Time and

90

CMOS

-

0.0000183

-

0.5

DualVth, TSRAM(tunneling based static random access memory)

Noise margins may in- crease

High speed tunneling,

low static and dynamic power dissipation,

high robustness

Read ac- cess time-

1ns,

Write ac-

cess

time=0.5ns

,

Array

size=32x32

Standby power

dissipation of 6x(10)-5

0.5 V Opera- tion,”[8]

mW per cell dynamic power dissipation of 1.8x (10)-7 mW per cell

Wagt van der J. P. A., Sea- baugh A.C., and Beam E.A., “RTD/HFET Low Standby Power SRAM Gain Cell,”[9]

HFET/RTD

-

-

-

0.4

Tunneling SRAM us- ing RTD(resonant tun- neling diodes), HFET(hetero structure field transistors)

Area over- heads

may in- crease

Reduced standby power consumption, more compact, low current density

Reduced standby power reduc- tion=50nW

, high speed, access

time=0.5ns

Author & Title

Technology

(nm)

Pow- er (µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Com- ments

Nod Kenji, Matsui Kou- jirou , Takeda Koichi, and Nakamura Nor- itsugu, “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-um Logic Technology,”[10]

180

CMOS

-

0.0019344

-

1.8

Concept of Loadless CMOS

Tradeoff between

cell size and SNM

Cell is com- pact.

High stability, high speed and high den- sity

Cell area is

35% small- er.

Arsovski Igor, Chan- dler Trevis and Sheikholeslami Ali, “A Ternary Content- Addressable Memory (TCAM) Based on 4T Static Storage and In- cluding a Current-Race Sensing Scheme,”[11]

180

CMOS

-

0.01754

-

1.2

Match-line (ML) sense scheme

Bitline can’t be high for a long pe- riod of time

Increase in density

Power con- sump- tion is less.

Noda K., Matsui K., Ito S., Masuoka S., Ka- wamoto H., Ikezawa N., Takeda K., Aimoto Y., Nakamura N., Toyo- shima H., Iwasaki T., and Horiuchi T., “An Ultra-High-Density High-speed Loadless Four-Transistor SRAM Macro with a Dual- Layered Wisted Bit- Line and a Triple-Well Shield,”[12]

180

CMOS

-

0.0019344

400

1.8

Dual-layered twisted bit- line,triple

well shield- ing

Memory capacity is less than embedded DRAM macros

Access speed and reliability is increased

Access time =

2.35 ns.

Bit-line

signal

delay is

re-

duced

by 20-

25%.

SNM >

400 mV

Takeda K., Aimoto Y., Nakamura N., Toyo- shima H., Iwasaki T., Noda K., , Matsui K., Itoh S., Masuoka S., Horiuchi T., Nakagawa A., Shimogawa K., and Takahashi H., “A 16-Mb

400-MHz Loadless

CMOS Four-Transistor

SRAM Macro,”[13]

180

CMOS

-

54.08

400

1.8

Uses end- point dual- pulse drivers, wordline- voltage-level compensa- tion circuit and all- adjoining twisted bit- line scheme

Smaller storage- node ca- pacitance and lower load- element current

Accurate tim- ing control, stable data retention,

bit-line cou- pling capaci- tance re- duced, high speed access and smaller size

Size is

66% of

Coven-

tional

6T

SRAM.

Access

time =

2.5 ns

Yang Jinshen, and Chen Li,“A New Loadless 4- Transistor SRAM Cell with a 0.18 µm CMOS Technology,”[14]

180

CMOS

-

-

-

1.8

Bitlines are precharged to ground in- stead of VDD

Tradeoff between

the cellsize and cell stability. Node

which is storing

logic high can’t retain its full swing val- ue because it is float- ing.

Consumes

less power

and less area

SNM =

446

mV,

Cell

layout

size is

15%

small-

er.

Highly stable

when cell ratio=3. Used in high speed and

high density SRAMs

.

Giraud B., Amara A., and Vladimirescu A., “A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation,”[15]

32

CMOS

-

-

-

1.2

Driverless (DL) SRAM cell

An extra back gate is required

Operating characteristics are improved, stability im- proved in read and re- tention mode, less access time

SNM >

350 mV

Access

time

de-

creased

by 50%

Area

de-

creased

by 30%

Batude P., Jaud M-A., Thomas O., Clavelier L., Pouydebasque A., Vinet M., Deleonibus S., and Amara A, “3D CMOS Integra- tion:Introduction of Dynamic coupling and Application to Compact and Robust 4T SRAM,”[16]

TCAD

-

-

-

1.1

3D Integra- tion Technol- ogy

Higher TB

is required

Stability and surface densi- ty increases, balance be- tween SNM and RNM improved

Leak- age current

=10

pA/µm

RNM =

320 mV

SNM =

150 mV

Density

Gain

=16.4%

Mazreah Azizi A., Sa- hebi Reza M., Manzuri Taghi M., Hosseini Ja- vad S., “A Novel Zero- Aware Four-Transistor SRAM Cell for High Density and Low Power Cache Application,”[17]

65

HSPICE

-

-

-

1.2

Uses two word-lines and one pair bit-line

Average leakage current is

15% great- er

High density and low pow- er, retains its data with leakage cur- rent and posi- tive feedback without re- fresh cycle

Aver- age delay access

is 30% small- er.

Aver- age dy-

namic energy con- sump- tion is

45% small- er.

SNM =

0.35 V

R Sandeep, Deshpande Narayan T, and Aswatha A R, “Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technolo- gies,”[18]

130 CMOS,

90 CMOS,

65 CMOS

-

-

333.33

1.5 (130

CMOS),

1.2 (90

CMOS)

and 1.1

(65

CMOS)

Bit-lines are precharged to ground

Read Ac- cess time is greater

Less power and less area, high stability

Capaci- tance

of each bitline

= 20 fF Load =

20 fF

Fan Ming-Long, Wu Yu-Sheng , Hu Vita Pi- Ho, Hsieh Chien-Yu, Su Pin, and Chuang Ching-Te, “ Compari- son of 4T and 6T Fin- FET SRAM Cells for Subthreshold Operation Considering Variabil- ity—A Model-Based Approach,”[19]

32 FinFET

-

-

-

0.4

Model-based approach to consider im- pact of device variation on stability

-

Better nomi- nal READ static noise margin (RSNM)

Area re- duced by

25%.

Degalahal V., Vi- jaykrishnan N., and Irwin M. J., “Analyzing Soft Errors in Leakage Optimized SRAM De- sign,”[20]

70

HSPICE

-

-

-

No VDD

4T SRAM

without VDD

Between optimizing leakage power and improving immunity

to soft er- ror

Leakage and area reduc- tion

Leak- age

re- duced by 60-

80% Advan- van- tage in area by

12-33%

Author & Title

Technology

(nm)

Power

(µW)

Ar- ea (mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Tran Hiep, “Demonstration

of 5T SRAM And

6T Dual-Port

RAM Cell Ar-

rays,”[21]

600

CMOS

-

-

-

2

Single bitline

SRAM cell

-

Can operate at dual-port memory over a wide voltage supply range,improved cell size

Can be used in high density SRAM.

Can be imple- ment in ASIC design.

Wieckowski M., and Margala M., “A Novel Five- Transistor (5T) Sram Cell For High Perfor- mance Cache,” [22]

180

TSMC

CMOS

-

0.00

67

-

1.8

Based on 7T

current-

mode

cell

-

High-speed, Low-power. Optimization in transistor sizes.

57%enhancement in speed, 12% power reduction and 6% area re- duction.

Mohan Nitin and Sachdev Manoj, “Novel Ternary Storage Cells And Techniques For Leakage Reduc- tion In Ternary Cam,”[23]

180

CMOS

-

-

-

1.8

Ternary Con- tent Ad- dressable Memories (TCAM)

Unused state can’t be stored in cell

Leakage reduc- tion, high speed, smaller area

Leakage de- creased by 32-

40%.

Cosemans S., Dehaene W., and Catthoor F., “A Low-Power Em- bedded SRAM

for Wireless Ap- plications,”[24]

180

CMOS

-

0.69

250

1.6

Short buff- ered bitlines

& memory databus,

Read opera- tion using dynamic stability,

Low-Swing Write Using Shared Low- Swing Re- ceivers, and Distributed Decoder

Large part of die used for on-chip signal monitoring circuits

Energy per access is re- duced, area reduced

Active power consumption reduced by fac- tor of 2.

Energy per ac- cess reduced to

54%

Energy = 9.5 pJ

Delay = 0.74 ns

Wieckowski M., and Margala M., “A Portless SRAM Cell Using Stunt- ed Wordline Drivers,”[25]

180

CMOS

-

0.00

877

-

1.8

Portless con- cept in an isolated test

cell

Some per- centage of current ratios in process results in slower operation

& reduce

efficiency

Higher SNM, less leakage, cell area re- duced

Static noise mar- gin increased by

22%.

Leakage de-

creased by 14%

Mazreaht Arash Azizi, Shalmani Mohammad

Taghi Manzuri, Noormande Reza, and Mehrparvar Ali, “A Novel Zero-Aware

Read-Static-

Noise-Margin-

Free SRAM Cell

for

High Density and

High Speed

Cache Applica-

tion,”[26]

250

CMOS

-

0.01961

-

2.5

Loop-cutting strategy, use one word- line and one bit-line dur- ing

read/write operation

-

Data is retained with leakage current and positive feed- back without refresh cycle

Cell size de- creased by 18%. Average delay is reduced by 20%. Average leakage current is 8% greater.

Nalam S., and Calhoun Benton H., “Asymmetric Sizing in a 45nm

5T SRAM to Im- prove

Read Stability over 6T,”[27]

45

CMOS

-

-

-

0.5

Novel asymmetric sizing ap- proach to increase read ability

Area and

Write

Noise

Margin

Robust read operation

Read stability and improved writability through write assist techniques.

Author & Title

Technol- ogy

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz

)

Vdd

(V)

Method- ology

Trade offs

Achievements

Comments

Narasimhan S.

,Chiel H.J., and

bhunia S., “Ultra- low-power and

Robust Digital- Signal-Processing Hardware for Im- plantable Neural Interface Microsys- tems,”[28]

70

HSPICE

10

0.21

33.33

0.6

Preferen- tial De- sign,NSPa lgo,power gat- ing,voltag

e scaling

Delay over- heads may

in- crease

Improved total energy, highrobust- ness,

high yield

Yield-79.94% Energy = 106.56 pJ Delay = 4.39 ns

Narasimhan S., and Bhunia Swarup, “Ultralow-Power

and Robust Embed- ded Memory for Bioimplantable Microsystems,”[29]

45

HSPICE

-

0.000256

00

0.0002

5600

0.8

Power gating technique

Noise mar- gins may in-

crease

Low energy dissipa- tion,betterarea, high robust- ness

Array size-(64x80)

Noise margin-Read=209

Write=420

Hold=383

It is 611x faster and 1.4x denser than subThresh-

old design. Energy = 33.72 pJ Delay = 0.37 ns

Elakkumanan Praveen,Thondapu Charan, and Sri- dhar Ramalingam, “A Gate Leakage Reduction Strategy For Sub-70nm Memory Cir- cuits,”[30]

65

BPTM

_

_

_

0.8

N- controlled SRAM using dual Vth (Dy- namic voltage scaling)

1-3% less perfor for- manc e.

Better leakage savings

60% reduction in gate leakage

Hua Chung-Hsien, Cheng Tung-Shuan, and Hwang Wei, “Distributed Data- Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM,”[31]

130

CMOS

-

-

-

1

Column and row co- controlled power gated SRAM

Extra AND gate delay

High robust- ness

SNM-340 mV, active power reductions (PDP)

32-bit-49%, 16-bit-75%

8-bit -93%,area overhead-

8.1%

Sridhara Srinivasa R., DiRenzo Mi- chael, Lingam Srinivas, Lee Seok- Jun, Blázquez Raúl, Mxey Jay, Ghanem Samer, Lee Yu- Hung, Abdallah Rami, Singh Prashant, and Goel Manish, “Micro- watt Embedded Processor Platform for Medical Sys- tem-on-Chip Ap- plications,”[32]

130

CMOS

5nW/kH

z(0.5)

19N

w/kHz(

0.1)

1.95 um sq bit cell or

1.3mm

sq

<1mh z

0.5- 1

Differen- tial SRAM,FF

T accelera-

tor

Leak- age pow- er,dy nam- icpow er,me mory band width

,run time

Less leakage, more reliable

90% effective dc-dc con- verter,

performance 7KHz(0.5v),

5MH(1v),

Leakage power

7nW(0.3v),

density of SRAM-32kb

Energy = 100 nJ

Kulkarni Jaydeep P., and Roy Kaushik, “Ul- tralow-Voltage Process-Variation- Tolerant Schmitt- Trigger-Based SRAM Design,”[33]

130

CMOS

-

1.063

270 kHz

300 mV

Schmitt- Trigger (ST)- SRAM with Feedback mecha- nism

Bit cell area in-

creas- es 2x.

better read- stability as well as better write-ability,

1.6 x higher read static noise margin,

2x higher write-trip- point,

Leakage current-0.372Ua

Rooseleer Bram, Cosemans Stefan, and Dehaene Wim, “A 65 nm, 850

MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dy- namic cell stability and a dual swing data link,”[34]

65

CMOS

25.2

0.48

850

1.0

Dual swing

data link on the GBLs,

High

threshold

voltage

cells,

Dynamic

decoder

with

merged

address

latches

Noise mar- gins may in-

crease

ultra low leak- age power and very

low active en- ergy consump- tion,

improved sta- bility,

high speed, improved ro- bustness

Memory size -256 kbit, Wordlength -32 bit,

Cell type- L = 60 nm, W =

120 nm

Energy = 4.3 pJ/access

Bansal Aditya, Mukhopadhyay Saibal, and Roy Kaushik, “Device- Optimization Tech- nique

for Robust and Low-Power FinFET SRAM Design in NanoScale

Era,”[35]

50

FinFET

-

-

-

1.0

FinFET

Ac- cess time and perfor for- manc e,stab ility

Minimized leakage cur- rent and drain capacitance

to on-current ratio,

high robust- ness,

65%SRAM leakage is reduced, improves cell read failure by

200times,Tox-1.2nm

Amelifard Behnam, Fallah Farzan, and Pedram Massoud, “Leakage Minimi- zation of SRAM Cells in a Dual-Vt and Dual-Tox Technology,”[36]

65

HSPICE

-

-

-

1.1

Dual Vt, Dual Tox

Area over- heads

,delay

Reduced leak- age power dissipation, improved per- formance

Power dissipation of SRAM array size-64x512 is reduced to 33%.

Power dissipation of SRAM array size-32x512 is reduced to 40%.

Vth-0.18v

Sharifkhani Mo- hammad and Sachdev Manoj, “An Energy Effi- cient 40 Kb SRAM Module With Ex- tended Read/Write Noise Margin in

0.13 um

CMOS,”[37]

130

CMOS

-

-

100

0.4 per cell

Virtual ground architec- ture

Ac- cess time may in-

crease

Low leakage current,energy efficient

,improved stability

28% noise margin en- hancement, size-40kb, leakage current-

27Pa/Cell,

area overhead 8%,

dynamic data stability

management. Energy = 7 pJ

Lakshminarayanan S., Joung J., Nara- simhan G., Kapre R., Slanina M., Tung J., Whately M., Hou C-L., Liao W-J., Lin S-C., Ma P-G., Fan C-W., Hsieh M-C., Liu F- C., Yeh K-L.,

Tseng W-C., and Lu

S.W., “Standby

PowerReduction

and SRAM Cell

Optimization for

65nm

Technology,”[38]

65

CMOS

-

-

-

1.0

Body bias- ing tech- nique

Sta- bility issues may arise

Reduced leak- age current, improved per- formance

Fast process corners, improved yield

Author & Title

Technology

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Jiao Hailong, and Kursun Volkan, “Low Power and Robust Ground Gated Memory Banks with Com- bined Write Assist Techniques,”[39]

65

CMOS

-

-

1000

1.2

Multi Threshold CMOS tech- nology

Careful transistor sizing,cell layout op- timization

Stronger

data stability

and lower

leakage pow-

er consump-

tion

write margin enhanced to

2.75x,

write delay

reduced to

71.70%,

data stability

increases by

2.11x,

leakage power

consumption

reduces by

65.38%.

cell layout area

is increased

upto 26.97%, electrical quali-

ty is enhanced by 9.36x

Liu Zhiyu and Kursun Volkan, “Characterization of a Novel Nine- Transistor SRAM Cell,”[40]

65

CMOS

-

-

-

-

Dual Vth technique

Area over- heads,

delay may increase

Improved performance, reduced leak- age power

Read SNM is improved by 2 times as com- pared to 6T SRAM,

Leakage power is reduced by

57%

Birla Shilpi, Shukla Neeraj Kr., Pattanaik Mani- sha, Singh R.K., “Device and Cir- cuit Design Chal- lenges for Low Leakage SRAM for Ultra Low Power Applica- tions,”[41]

90

CMOS

-

-

-

0.5

A data pro- tection

NMOS tran- sistor is add- ed.

1)write-

write mar-

gin

decreases

with de-

creasing

Vdd.

2)Read -

storage data

destruction

Vdd min-

440mV,

Access time-

20ns,

Better cell

performance,

Improved

write margin

It may achieve high speeds,Leakage power is re- duced by 21%

Yadav Monika, and Akashe Shyam, “New Technique For Reducing Sub- Threshold Leak- age In SRAM,”[42]

180

CMOS

-

-

-

1.8

Sense

Amplifiers

Layout op- timization

Lower leak- age current and power consumption

Area overhead increases by

16%,

47.5% better

power saving

Takeda Koichi, Hagihara Yasuhi- ko, Aimoto Yo- shiharu, Nomura Masahiro, Naka- zawa Yoetsu, Ishii Toshio, and Koba- take Hiroyuki, “A Read-Static-

Noise-Margin- Free SRAM Cell for Low-VDD and High-Speed Ap- plications,”[43]

90

CMOS

-

-

-

0.5

Read-static- noise- margin-free SRAM

cell

Leakage current in- creases with temperature

Low Vdd and high speed operation. Smaller area, SNM is im- proved

Area is 23%

smaller

Access time is

20ns

P Rajeev Anand., and P Chandra Sekhar., “Reduce Leakage Currents in Low Power

90

CMOS

9.738

0.000041600

-

1.0

Dual-VTH and trans- mission gate technique

Read Access time in- creases

Leakage cur- rent decreas- es,

reduced static power dissi-

Leakage cur- rent=133nA, gate current leakage reduc- es by 58%,

SRAM cell Struc- tures,”[44]

pation

static noise margin reduces by 10%

Author & Title

Tech- nology

(nm)

Pow er (µW

)

Area

(mm2)

Fre q (M

Hz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Kim Tea-Hyoung, Liu J., and Kim C.H., “An 8T sub- threshold SRAM Cell Utilizing Re- verse Short Chan- nel Effect for Write Margin and Read Performance Im- provement,”[45]

130C MOS

-

0.000006

3648

-

1.2

Reverse short channel effect

Leakage cur- rent increas- es,

gate capaci- tance increas- es

Improved read and write margin, reduced threshold volt- age

52% speedup ,

area overhead

20%,

Ion/Ioff improved

from 169 to 271,

3x longer channel

length,

no extra circuitary

required

Verma N., and

Chandrakasan

A.P., “A 256 kb 65

nm 8T Subthresh-

old SRAM Em-

ploying Sense-

Amplifier Redun-

dancy,”[46]

65

CMOS

2.2

-

0.02

5

0.35

Sense amplifier redundancy

Increased device sizing and its statis- tical offset

High density, minimum

operating voltage,more read write stability,

low leakage power dissipa- tion

Leakage power saving 10x,

array size (256x128),30% area overhead

Wang Bo, Zhou Jun, and Kim Tony T., “Maximization of SRAM Energy Efficiency Utilizing MTCMOS Tech- nology,”[47]

65

CMOS

-

-

-

0.4

Multi Threshold CMOS technol- ogy

Read,write delays may increase.

High energy efficiency,

better perfor- mance

Array structure-

256 rows x 128

columns,

33% incease in

energy efficiency.

Kwong Joyce, Ramadass Yogesh K., Verma Naveen, and Chandrakasan Anantha P., “A 65 nm Sub-Vt Micro- controller With Integrated SRAM and Switched Ca- pacitor DC-DC Converter,”[48]

65

CMOS

-

-

-

0.5

Timing pro- cess,subVt mi- crocontroller with sub threshold memory

Area may increase

Leakage power and energy is reduced, improved sta- bility

Array size-128kb,

1uW standby

power at 300 mV,

dc-dc converter

achieves 75% effi-

ciency

Energy = 27.2 pJ

Liu Zhiyu and Kursun Volkan, “Characterization

of a Novel Nine- Transistor SRAM Cell,”[40]

65

CMOS

-

-

-

-

Alternative communication channel (composed of a separate read bitline and the transistor stack) used for

reading the data

from the cell

Area over- head,delay may increase

Improved data stability

It may achieve high speeds. Leakage power is reduced by 23%.

Jain Sanjeev K., and Agarwal P., “A Low Leakage and SNM Free SRAM Cell Design in Deep Sub micron CMOS Technolo- gy[49]

90

CMOS

-

-

-

1.1

1 transistor re- duces gate leak- age and other makes cell SNM free.

Degradation

in read access

time when

read = ‘0’

Reduction in gate leakage power. Cell area increases.

Total leakage re- duced by 50.2%. SNM free when read = logic 0.

SNM improved by

2.2 times.

Increase in cell

area is 30%.

Author & Title

Tech nology (nm)

Pow er (µW

)

Area

(mm2)

Freq (MH z)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Ramani Ram- nath Arun, and Choi Ken, “A Novel 9T SRAM Design in Sub- Threshold Region,”[50]

45

HSPICE

-

-

-

0.3

Sub threshold technique

Degradation in perfor- mance

Leakage power reduction,

improved read

,write margin

Saving of PDP (write)- 2.80% <7T SRAM, 4.48 % <

8T SRAM , 5.64%

<9T SRAM

8.5 % <11T SRAM. (read)- 44.8 % <7T

SRAM

66.18 % <9T SRAM

Razavipour

G., Kusha

Afzali A., and

Pedram M.,

“Design and

Analysis of

Two Low

Power SRAM

Cell Struc-

tures,”[51]

45

HSPICE

-

-

-

0.8

Dual Vth tech- nique

Access time increases

Reduced static power dissipation and high perfor- mance

1st cell-Gate leakage current decreases by 66%,

Ideal power de- creases by 58%,

2nd cell--Gate leak- age current de- creases by 27%, Ideal power de- creases by 37%, Channel length- pmos=0.4um,NMO S=0.2um

Mali Madan, Dr. Sutaone M.S., Bhalerao Mangesh, and Tak Shital, “Deep Submi- cron Imple- mentation of Gating Tran- sistor Power Saving Tech- nique for Power Opti- mized Code Book SRAM,”[52]

250

SPICE

-

-

-

0.6

Attachement of extra row and column to SRAM

Area in- creases with decrease in power

Improved reliabil- ity,

Access time,

power dissipation

is reduced ,

Access time reduc- es by 2ns, array size-256*8 ,

density -32kb,

bit line length-1mm

max,

no metal layers-3,

Power Dissipation reduced to 13%

Masuda Cho- taro, Hirose Tetsuya, Matsumoto Kei, Osaki Yuji, Kuroki Nobutaka,

and Numa Masahiro, “High Cur- rent Efficiency Sense Ampli- fier Using Body-Bias Control for Ultra-Low- Voltage SRAM,”[53]

350

SPICE

-

-

0.003

33

0.5

current latch sense amplifier with a current- reuse technique

Power dissi- pation may increase

High speed pre charging,

improved perfor- mance,

small overhead

pre-charge time decreased by 86.9%

,

power dissipation

increased by 8.6%,

Clark Law- rence T., Mor- row Michael and Brown William, “Re- verse-Body Bias and Sup- ply Collapse for Low Effec- tive Standby Power,”[54]

130

CMOS

165

125000

000000

0

0.032

1

Reverse body bias (RBB), voltage collapse technique

Area may increase

Low power dissi- pation,

high efficiency, cost remains same

Easy to design RBB, density-34kb,83% stand by power reduction

Liu Zhiyu and Kursun Volkan, “Characteri- zation of a Novel Nine- Transistor SRAM Cell,”[40]

65

CMOS

-

-

2000

1

Two separate data access mechanisms for the read and write opera- tions.

Area may increase.

Improved data stability and leak- age power reduc- tion.

It may be used for high speed circuits. leakage power is reduced by 51%.

Singh R., Pat- tanaik M., and Shukla N., “Characteri- zation of a Novel Low- Power SRAM Bit-Cell Struc- ture at Deep Sub-Micron CMOS Tech- nology for Multimedia Applica- tions,”[55]

45

CMOS

-

-

-

0.8

IP3 SRAM bit- cell

Area and performance

Reduced power dissipation, Improved stability

tOX = 2.4 nm, Vthn

= 0.224 V, Vthp =

0.24V at T =

27°C.during write-

IP3 cell demands

17.65% and 41.53%

less power as com-

pared to 6T and PP

cells.

Author & Title

Tech- nology (nm)

Pow er (µW

)

Area

(mm2)

Fre q (M

Hz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Saripalli Vinay, Datta Suman, Narayanan Vi- jaykrishnan, and Kulkarni

Jaydeep P.,

“Variation-

Tolerant Ultra

Low-Power

Heterojunction

Tunnel FET

SRAM De-

sign,”[56]

45

TCAD

-

-

-

<3

00mV

TFET (tunnel FET) Schmitt- Trigger (ST)- SRAM with Feedback mechanism

Stability issues

Improved read/write noise margins,

lowenergy, improved perfor- mance,

can operate at low

Vcc.

Improved varia- tion tolerance,

1.2x reduction in dynamic energy,

13x reduction in leakage power

Calhounand Benton High- smith and Chandrakasan Anantha P., “A

256-kb 65-nm

Sub-threshold

SRAM Design

for Ultra-Low-

Voltage Opera-

tion,”[57]

65

CMOS

3.28

-

0.47

5

0.3

Separate read and write word line

Speed may decrease

Improved cell sta- bility,

better noise mar- gins,

power and energy saving

It saves 2.5x and

3.8x in leakage

power by scaling

from 0.6v to 0.4v

Ebrahimi Amir, Kargaran Ehsan and Golmakani Abbas,“Design and Analysis of Three New SRAM

Cells,”[58]

130

HSPICE

9.37

-

-

0.32

Separate read and write word line

Area overheads

Better SNM,

reduced leakage

current

512 cells per bit line and 128 col- umn cell array is achieves better read and write

Lo Cheng-Hung and Huang Shi- Yu,“P-P-N

Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation,”[59]

90

CMOS

-

-

0.9

0.32

Cross coupled P-P-N inverter pair

Area overheads

Low cell leakage, high noise immuni- ty,

ability to operate at low voltage,

high density

High immunity to data depend- ent bit line leak- age

Moradi Farshad

, Wisland Dag

T., Mahmoodi

Hamid, Berg

Yngvar, and

Cao. Tuan Vu,

“New SRAM

Design Using

Body Bias Tech-

nique for Ultra

Low Power Ap-

plications,”[60]

65

-

-

-

0.3

Body biasing technique

Area overheads may in- crease

Low power dissi- pation,

ultra supply volt-

age scaling,

SNM improvemnt

Static noise mar- gin is improved by 15%, Improvement in SNM of READ cycle-22%

Author & Title

Tech- nology

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Moradi Farshad, Wisland Dag.T., Aunet Snorre, Mahmoodi Hamid and Cao Tuan Vu, “65nm Sub- Threshold 11T- SRAM for Ultra Low Voltage Ap- plications,”[61]

65

CMOS

-

-

-

0.2

Boost capaci- tor (CB)

is used

Area may increase

Higher SNM and higher speed

Area overhead between 22 -28%,

4x improvement in read speed

Ebrahimi Amir, Kargaran Ehsan and Golmakani Abbas,“Design

and Analysis of Three New SRAM Cells,”[58]

130

CMOS

6.29

-

-

0.27

Separate

read and

write word

line

Area overheads

Better SNM, reduced leak- age current

512 cells per bit line and 128 col- umn cell array is achieves better read and write

Singh Ajay Kumar, Prabhu C.M.R., Pin Soo Wei and Hou Ting Chik, “A Pro- posed Symmetric and Balanced 11-T SRAM Cell for lower power con- sumption,”[62]

250

CMOS

-

-

-

2.5

Two tail transistors

are used

Write access delay increased

Low circuit activity fac- tor,

Low active power densi- ty,

reduced

power con- sumption

Consumes 40% less average pow- er,

7% slower during write operation

Lin Sheng, Kim Yong-Bin, and Lombardi Fabrizio, “A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors,”[63]

32

CMOS

-

0.3764

-

0.9

Hardening approach

Speed

and sta-

bility is-

sues

Power delay product re- duction.

soft error tolerance im- proved

Superior re- sistance to soft errors,

high performance

Chiu Yi-Wei, Hu Yu-Hao, Tu Ming- Hsien, Zhao Jun- Kai, Jou Shyh-Jye and Chuang Ching-Te, “A 40 nm 0.32 V 3.5 MHz

11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data- Aware Write- Assist,”[64]

40

CMOS

-

-

3.5

0.32

Bit interleav- ing with data aware power cut off

Area overhead may in- crease

Improved write ability, can work at very low Vdd

Leakage pow- er=13.5uW Switching ener- gy=0.49pJ

Author & Title

Technology

(nm)

Power

(µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Mall Ambrish, Singh Suryabhan Pratap, Mishra Manish and Sri- vastava Geeti- ka,“Analysis Of

12T SRAM CELL For Low Power Application,”[65]

45

CMOS

-

-

-

0.4

Data reten- tion p gated, Series con- nected tail transistors

Area over- heads

may in- crease

Low power dissipation, reduced leak- age current, low energy consumption

Transistor width=100nm, Power reduction by 45.94%

Chen Hu, Jun Yang, Meng Zhang and Xiulong Wu, “A

12T subthreshold SRAM Bit-cell for Medical Device Application,” [66]

130

CMOS

-

-

-

0.4

Schmitt Trig- ger based SRAM

Robustness issues may arrive

High stability, more robust- ness

Power consump- tion reduces to

16%,

30.2% grater hold

margin,

45% better SNM

Shayan Md, Singh Virendra, Singh Adit D and Fujita Masahiro, “SEU Tolerant Robust Memory Cell De- sign,”[67]

130

CMOS

-

-

-

1.2

SEU(single event upset) Tolerant SRAM

Reliability may re- duce,

area over- heads may increase

High robust- ness,

high perfor- mance,

more eco- nomical

62x increase in

Qcritical ,

It does not flip

transient pulse

,α=0.2ns,β=0.05ns

Author & Ti- tle

Tech- nology

(nm)

Po wer

(µ W)

Ar ea

(m m2)

Fre q

(M Hz)

V

dd

(V)

Method- ology

Trade offs

Achieve- ments

Comments

Sriram K V, Ranganna Ramappa Naik, Pavan Nandan S G and Kendaganna Swamy, “Design Of Low Power

64-Bit SRAM Using 13T Cell,”[68]

180

CMOS

283.33

-

-

1.1

Single read/write architecture, Stack tech- nique

Area overheads may in- crease

High perfor- mance, improved noise margin, low power consumption

Power consump- tion-

static=283.14uW dynamic=161.273uw Static noise margin- read SNM=0.70v write SNM=0.685v

Author & Title

Tech- nology (nm)

Pow- er (µW)

Area

(mm2)

Freq

(MHz)

Vdd

(V)

Methodology

Trade offs

Achievements

Comments

Fujiwara Hidehi- ro, Okumura Shunsuke, Iguchi Yusuke, Noguchi Hiroki, Kawagu- chi Hiroshi and Yoshimoto Masahiko, “A

7T/14T Dependa- ble SRAM and Its Array Structure to Avoid Half Selection,”[69]

65

CMOS

-

-

-

0.26

Quality of bit

Larger β ratio, SNM may in- crease

Improved relia- bility, speed.

Read and write operations are improved

SRAM works in

3 modes-

normal,

high speed,

dependable

Yoshimoto Shusuke, Ama- shita Takuro, Okumura Shun- suke, Yamaguchi Kosuke, Yo- shimoto Masahiko, and Kawaguchi Hiro- shi, “Bit Error and Soft Error Hardenable

7T/14T SRAM with 150-nm FD- SOI Process,”[70]

150

TCAD

-

-

-

0.1

FD-SOI

Between area (cost) and reli- ability

Improved BER (Bit Error Rate), SER (Soft Error Rate) and relia- bility.

Improved mini- mum operating voltage

Alpha-induced SER suppressed by 80%

Neutron- induced SER decreased by

34.4%

Qcrit increased by 10-70%

14Tsuperior than 7T

Nakata Yohei, Ito Yasuhiro, Sugure Yasuo, Oho Shi- geru, Takeuchi Yusuke, Okumu- ra Shunsuke, Kawaguchi Hiro- shi, and Yo- shimoto Masahiko,

“Model-Based Fault Injection for Failure Effect Analysis– Evaluation of Dependable SRAM for Vehi- cle Control Units,”[71]

65

CMOS

-

-

-

0.4-

0.8

Fault Injec- tion System

Dependability of SRAM af- fects dependa- bility of pro- cessor system

System level de- pendability im- proves.

Area overhead is 11% greater. Has 2 modes – normal mode and dependable mode.

Vmin improved

by 0.05–0.15 V

Jinwook Jung, Yohei Nakata, Shunsuke Oku- mura, Hiroshi Kawaguchi, and Masahiko Yo- shimoto, “256-KB Associativity- Reconfigurable Cache with

7T/14T SRAM for Aggressive DVS Down to 0.57

V,”[72]

65

CMOS

-

-

-

0.115

Associativity- reconfigura- ble cache. Consists of pair of cache ways.

2 pmos tran- sistors are added

Performance decrease.

area overhead is increased

Reliability en- hance

Possesses scala- ble characteris- tic of reliability. Area overhead increased by

1.91% and

5.57% in 32-KB

and 256-KB

caches,

It has 2 modes-

normal mode

and dependable mode

Jinwook Jung, Yohei Nakata, Shunsuke Oku- mura, Hiroshi Kawaguchi, and Masahiko Yo- shimoto, “A Vari- ation-Aware 0.57- V Set-Associative Cache with Mixed Associa- tivity Using

7T/14T SRAM,”[73]

65

CMOS

-

2.04

-

0.57 in

de- penda ble mode

Induced de- fective SRAM cells, 2 pmos transistors are added andmixed associativity scheme is used

Area overhead, Don’t have sufficient op- erating mar- gins

Minimum oper- ating voltage (Vmin) is re- duced,

reliability im- proves

Reduced Vmin by 80 mV with- in 7.81% capaci- ty and 5.22% area overhead.

It has 2 modes - normal mode and dependable mode

Yamaguchi Kosuke, Okumu- ra Shunsuke, Yoshimoto Masahiko, and Kawaguchi Hiro- shi, “0.42-V 576- kb 0.15-µm FD- SOI SRAM with

7T/14T Bit Cells and Substrate Bias Control Cir- cuits for Intra-Die and Inter-Die Variability Com- pensation,”[74]

0.15

FD-

SOI

-

-

-

0.42

FD-SOI substrate bias control mech- anism.

Process varia- tions may af- fect the sys- tem.

Maximizes the operating mar- gin,

retention voltage is reduced

Two operating modes - normal mode and de- pendable mode. Minimum re- tention is re- duced to 0.28 V

Nakata Yohei , Okumura Shun- suke , Kawaguchi Hiroshi , and Yoshimoto Masahiko, “0.5-V Operation Varia- tion-Aware

Word-Enhancing Cache Architec- ture Using

7T/14T hybrid

SRAM,” [75]

65

-

-

-

0.5

Variation aware word enhancing scheme

Extra control lines are re- quired

Improved relia- bility and control lines,

Low power con- sumption

Suitable for dynamic volt- age and fre- quency scal- ing(DVFS), Power reduc- tions are 90% and 65%