ABSTRACT
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. With the fast advancement of CMOS fabrication technology,more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. Wide
spread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). This has recently generated a great
demand for low-power, low-voltage ADCs that can be realized in a mainstream deep-submicron CMOS technology. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also
imaging, instrumentation systems. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing
process and improved the resolution and design specially power consumption .The ADC designed is carried out by designing each building block
of the circuit separately and then assembling them together to get the required ADC. The CMOS comparator, the digital to analog converter (DAC) and the successive approximation register (SAR)
are the key elements in the design of the ADC. The CMOS operational amplifier was designed with a high unity gain frequency that will direct the ADC to operate at a greater speed.Design has been carried out in Tanner EDA tools.We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications
applications.The ADC chip uses the phase modulation–
demodulation architecture and on-chip digital filtering.The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as well as decimation digital
filter, have been redesigned for operation at 20 GHz. Test results of this 6000 Josephson junction 2G ADC chip at clock frequencies up to 19.6 GHz are described.There are many different types of ADC structures, one of these is the Pipelined ADC, which is characterised by having relative high
speed, with a low area- and power consumption.
The pipelined ADC design was achieved by initially analysing the di®erent options regarding the overall structure. The 1.5-bit stage resolution is chosen
in order to accommodate the speed requirements. The ¯nal overall structure is with 8 1.5-bit stages
and one 2-bit stage, so that digital error correction can be applied.
Further analysis of the structure of the stage structure concluded
that an redesign of the traditional structure into a subADC/MDAC
structure would be advantages. Generally the design is fully
differential in order to compensate for offset errors and other
limitations.
As technology scales, the improved speed and energy efficiency
make the successive-approximation-register (SAR) architecture an
attractive alternative for applications that require high-speed and
high-accuracy analog-to-digital converters (ADCs). In SAR ADCs,
the key linearity and speed limiting factors are capacitor mismatch
and incomplete digital-to-analog converter (DAC)/reference voltage
settling. In this thesis, a sub-radix-2 SAR ADC is presented with
several
new
contributions.
The
main
contributions
include
investigation of using digital error correction (redundancy) in SAR
ADCs for dynamic error correction and speed improvement,
development of two new calibration algorithms to digitally correct
for manufacturing mismatches, design of new architecture to
incorporate
redundancy
within
the
architecture
itself
while
achieving 94% better energy efficiency compared to conventional
switching algorithm, development of a new capacitor DAC structure
to improve the SNR by four times with improved matching, joint
design of the analog and digital circuits to create an asynchronous
platform in order to reach the targeted performance, and analysis
of key circuit blocks to enable the design to meet noise, power and
timing requirements.
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